W25Q80DLSNIG

W25Q80DV/DL 2.5V AND 3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date:October 02, 2015 - 1 - Preli mry-Revision H W25Q80DV/DL Table of Contents 1. GENERAL DESCRIPTION ......................................................................................................... 5 2. FEATURES ................................................................................................................................. 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS..................................................................... 6 3.1 Pin Configuration SOIC 150-MIL/208-mil AND VSOP 150-mil: ...................................... 6 3.2 Pad Configuration WSON 6x5-mm, USON 2X3-mm...................................................... 6 3.3 Pin Configuration PDIP 300-mil ...................................................................................... 7 3.4 Pin Description SOIC/VSOP , WSON/USON & PDIP 300-mil ....................................... 7 3.5 Ball Configuration WLCSP .............................................................................................. 8 3.6 Ball Description WLCSP ................................................................................................. 8 4. PIN DESCRIPTIONS .................................................................................................................. 9 4.1 Chip Select (/CS) ............................................................................................................ 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ............................... 9 4.3 Write Protect (/WP) ......................................................................................................... 9 4.4 HOLD (/HOLD)................................................................................................................ 9 4.5 Serial Clock (CLK) .......................................................................................................... 9 5. BLOCK DIAGRAM .................................................................................................................... 10 6. FUNCTIONAL DESCRIPTION.................................................................................................. 11 6.1 SPI OPERATIONS ....................................................................................................... 11 6.1.1 Standard SPI Instructions ............................................................................................... 11 6.1.2 Dual SPI Instructions ...................................................................................................... 11 6.1.3 Quad SPI Instructions ..................................................................................................... 11 6.1.4 Hold Function .................................................................................................................. 11 6.2 WRITE PROTECTION .................................................................................................. 12 6.2.1 Write Protect Features .................................................................................................... 12 7. CONTROL AND STATUS REGISTERS ................................................................................... 13 7.1 STATUS REGISTER .................................................................................................... 13 7.1.1 BUSY .............................................................................................................................. 13 7.1.2 Write Enable Latch (WEL) .............................................................................................. 13 7.1.3 Block Protect Bits (BP2, BP1, BP0) ................................................................................ 13 7.1.4 Top/Bottom Block Protect (TB) ....................................................................................... 13 7.1.5 Sector/Block Protect (SEC) ............................................................................................. 13 7.1.6 Complement Protect (CMP) ............................................................................................ 14 7.1.7 Status Register Protect (SRP1, SRP0) ........................................................................... 14 7.1.8 Erase/Program Suspend Status (SUS) ........................................................................... 14 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ................................................................... 14 7.1.10 Quad Enable (QE) ........................................................................................................ 15 7.1.11 Status Register Memory Protection (CMP = 0) ............................................................. 16 7.1.12 Status Register Memory Protection (CMP = 1) ............................................................. 17 8. INSTRUCTIONS ....................................................................................................................... 18 8.1 Manufacturer and Device Identification ........................................................................ 18 (1) 8.2 Instruction Set Table 1 (Standard SPI Instructions) .................................................. 19 8.3 Instruction Set Table 2 (Dual SPI Instructions) ............................................................. 20 8.4 Instruction Set Table 3 (Quad SPI Instructions) ........................................................... 20 8.5 Instruction Descriptions ................................................................................................ 22 Publication Release Date:October 02, 2015 - 2 - Preli mry-Revision H