W25Q64JVZEIM

W25Q64JV-DTR 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI & DTR For Industrial & Industrial Plus Grade Publication Release Date: March 27, 2018 Revision J W25Q64JV-DTR Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 4 2. FEATURES ....................................................................................................................................... 4 NOTE: 1. HARDWARE /RESET PIN IS ONLY AVAILABLE ON TFBGA OR SOIC16 PACKAGES ........... 4 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 5 3.1 Pin Configuration SOIC 208-mil ........................................................................................... 5 3.2 Pad Configuration WSON 6x5-mm / 8x6-mm, XSON 4x4-mm ............................................ 5 3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm, XSON 4x4-mm ......................... 5 3.4 Pin Configuration SOIC 300-mil ........................................................................................... 6 3.5 Pin Description SOIC 300-mil ............................................................................................... 6 3.1 Ball Configuration TFBGA 8x6-mm ...................................................................................... 7 3.2 Ball Description TFBGA 8x6-mm ......................................................................................... 7 4. PIN DESCRIPTIONS ........................................................................................................................ 8 4.1 Chip Select (/CS) .................................................................................................................. 8 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 8 4.3 Write Protect (/WP) ............................................................................................................... 8 4.4 HOLD (/HOLD) ..................................................................................................................... 8 4.5 Serial Clock (CLK) ................................................................................................................ 8 4.6 Reset (/RESET) .................................................................................................................... 8 5. BLOCK DIAGRAM ............................................................................................................................ 9 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 10 6.1 SPI / QPI Operations .......................................................................................................... 10 Standard SPI Instructions ..................................................................................................... 10 Dual SPI Instructions ............................................................................................................ 10 Quad SPI Instructions ........................................................................................................... 11 QPI Instructions .................................................................................................................... 11 SPI / QPI DTR Read Instructions .......................................................................................... 11 Hold Function ........................................................................................................................ 11 Software Reset & Hardware /RESET pin .............................................................................. 12 6.2 Write Protection .................................................................................................................. 13 Write Protect Features .......................................................................................................... 13 7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 14 7.1 Status Registers ................................................................................................................. 14 Erase/Write In Progress (BUSY) Status Only ................................................................. 14 Write Enable Latch (WEL) Status Only ........................................................................... 14 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable ................................. 14 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable ........................................ 15 Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable ........................................ 15 Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................ 15 - 1 -