A3T2GF30CBF-JRI

Doc. No. DSA3T2GF340CBFF.06 A3T2GF30CBF/A3T2GF40CBF 2Gb DDR3/DDR3L SDRAM d 2Gb DDR3/DDR3L SDRAM Specification Specifications Features Density: 2G bits The high-speed data transfer is realized by the 8 bits Organization prefetch pipelined architecture o 8 banks x 32M words x 8 bits Double data-rate architecture: two data transfers per o 8 banks x 16M words x 16 bits clock cycle Package Bi-directional differential data strobe (DQS and /DQS) o 78-ball FBGA is transmitted/received with data for capturing data at o 96-ball FBGA the receiver o Lead-free(RoHS compliant) and Halogen-free DQS is edge-aligned with data for READs center Power supply: aligned with data for WRITEs -HP Differential clock inputs (CK and /CK) o VDD, VDDQ = 1.35 V (1.283 to 1.45 V) DLL aligns DQ and DQS transitions with CK transitions o Backward compatible with DDR3 operation Commands entered on each positive CK edge data VDD, VDDQ = 1.5 V (1.425 to 1.575 V) and data mask referenced to both edges of DQS -JR Data mask (DM) for write data o VDD, VDDQ = 1.5 V (1.425 to 1.575 V) Posted CAS by programmable additive latency for -JRL better command and data bus efficiency o VDD, VDDQ = 1.35 V (1.283 to 1.45 V) On-Die Termination (ODT) for better signal quality Data Rate: 1866 Mbps /2133 Mbps (max.) o Synchronous ODT 1KB page size (x8) o Dynamic ODT o Row address: AX0 to AX14 o Asynchronous ODT o Column address: AY0 to AY9 Multi Purpose Register (MPR) for pre-defined pattern 2KB page size (x16) read out o Row address: AX0 to AX13 ZQ calibration for DQ drive and ODT o Column address: AY0 to AY9 Programmable Partial Array Self-Refresh (PASR) Eight internal banks for concurrent operation RESET pin for Power-up sequence and reset function Burst lengths(BL): 8 and 4 with Burst Chop(BC) SRT(Self Refresh Temperature) range: Burst type(BT) o Normal/Extended o Sequential (8, 4 with BC) Auto Self-Refresh (ASR) o Interleave (8, 4 with BC) Programmable output driver impedance control CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14 JEDEC compliant DDR3/DDR3L CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10 Row-Hammer-Free (RH-Free): detection/blocking Precharge: auto precharge option for each burst circuit inside access Driver strength: RZQ/7, RZQ/6 (RZQ = 240 ) Refresh: auto-refresh, self-refresh Average refresh period o 7.8 us at TC +85 o 3.9 us at TC > +85 Operating temperature range o TC = 0C to +95C (Commercial grade) o TC = -40C to +95C (Industrial grade) o TC = -40C to +105C (Automotive grade) Key Timing Parameters Speed Grade Data Rate(Mbps) CL nRCD nRP 1, 2, 3 -JR 2133 14 14 14 1, 2 -HP 1866 13 13 13 Notes: 1. Backward compatible to 1333, CL-nRCD-nRP = 9-9-9 2. Backward compatible to 1600, CL-nRCD-nRP = 11-11-11 3. Backward compatible to 1866, CL-nRCD-nRP = 13-13-13 Rev. 06 Oct. 14, 2020 1 of 50 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3T2GF340CBFF.06 A3T2GF30CBF/A3T2GF40CBF 2Gb DDR3/DDR3L SDRAM d Table of Contents 2Gb DDR3 SDRAM Specification ....................................................................................................................... 1 1. Ordering Information ............................................................................................................................ 3 2. Package Ball Assignment ....................................................................................................................... 4 3. Package outline drawing........................................................................................................................ 5 4. Electrical Specifications ......................................................................................................................... 7 5. Block Diagram ..................................................................................................................................... 30 6. Pin Function ........................................................................................................................................ 31 7. Command Operation ........................................................................................................................... 33 8. Functional Description ......................................................................................................................... 37 Rev. 06 Oct. 14, 2020 2 of 50 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.