A3R1GE40JBF-8E

Doc. No. DSA3R1GE340JBFF.04 A3R1GE30JBF/A3R1GE40JBF 1Gb DDR2 SDRAM 1Gb DDR2 SDRAM Specification Specifications Features Density: 1G bits Double data-rate architecture: two data transfers per Organization clock cycle o 8 banks x 16M words x 8 bits The high-speed data transfer is realized by the 4 bits o 8 banks x 8M words x 16 bits prefetch pipelined architecture Package Bi-directional differential data strobe (DQS and /DQS) is o 60-ball FBGA (x8) transmitted/received with data for capturing data at the o 84-ball FBGA (x16) receiver o Lead-free(RoHS compliant) DQS is edge-aligned with data for READs center- aligned Power supply with data for WRITEs o V ,V =1.7 to 1.9V DD DDQ Differential clock inputs (CK and /CK) Data Rate: 1066Mbps/800Mbps DLL aligns DQ and DQS transitions with CK transitions 1KB page size (x8) Commands entered on each positive CK edge data and o Row address: AX0 to AX13 data mask referenced to both edges of DQS o Column address: AY0 to AY9 Data mask (DM) for write data 2KB page size (x16) Posted CAS by programmable additive latency for better o Row address: AX0 to AX12 command and data bus efficiency o Column address: AY0 to AY9 On-Die-Termination for better signal quality Eight internal banks for concurrent operation Programmable RDQS, /RDQS output for making x8 Interface: SSTL 18 organization compatible with x4 organization o Burst lengths (BL): 4 , 8 /DQS, (/RDQS) can be disabled for single-ended Data Burst type (BT): Strobe operation o Sequential Off-Chip Driver (OCD) impedance adjustment is not o Interleave supported CAS latency (CL): 3, 4, 5, 6, 7 Precharge: Auto precharge option for each burst access Driver strength: Normal/Weak Low self-refresh current (IDD6) parts are available Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms o Average auto-refresh period 7.8us at TC +85 3.9us at TC > +85 Automotive grade 3 compliant with AEC-Q100 grade 3 Automotive grade 2 compliant with AEC-Q100 grade 2 Operating case temperature range o TC = 0C to +85C (Commercial grade) o TC = -40C to +95C (Industrial range) o TC = -40C to +95C (Automotive grade 3) o TC = -40C to +105C (Automotive grade 2) Rev. 04 Oct. 13, 2020 1 of 25 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3R1GE340JBFF.04 A3R1GE30JBF/A3R1GE40JBF 1Gb DDR2 SDRAM Table of Contents 1Gb DDR2 SDRAM Specification ....................................................................................................................... 1 1. Ordering Information ............................................................................................................................ 3 2. Package Ball Assignment ....................................................................................................................... 4 3. Package outline drawing........................................................................................................................ 5 4. Electrical Specifications: ........................................................................................................................ 7 5. Block Diagram ..................................................................................................................................... 15 6. Pin function ......................................................................................................................................... 16 7. Command Operation ........................................................................................................................... 18 8. Functional Description ......................................................................................................................... 19 Rev. 04 Oct. 13, 2020 2 of 25 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.