A3R12E30DBF-8E

Doc. No. DSA3R12E340DBFF.03 A3R12E30DBF/A3R12E40DBF 512Mb DDR2 SDRAM 512Mb DDR2 SDRAM Specification Specifications Features Density: 512M bits Double-data-rate architecture two data transfers per clock Organization cycle The high-speed data transfer is realized by the 4 bits 16M words 8 bits 4 banks (A3R12E30DBF) prefetch pipelined architecture 8M words 16 bits 4 banks (A3R12E40DBF) Bi-directional differential data strobe (DQS and /DQS) is Package transmitted/received with data for capturing data at the 60-ball FBGA(BGA) (A3R12E30DBF) receiver 84-ball FBGA(BGA) (A3R12E40DBF) DQS is edge-aligned with data for READs center- Lead-free (RoHS compliant) aligned with data for WRITEs Power supply: VDD, VDDQ 1.8V 0.1V Differential clock inputs (CK and /CK) Data rate: 1066Mbps/800Mbps (max.) DLL aligns DQ and DQS transitions with CK transitions 1KB page size (A3R12E30DBF) Commands entered on each positive CK edge data and Row address: A0 to A13 data mask referenced to both edges of DQS Column address: A0 to A9 Data mask (DM) for write data 2KB page size (A3R12E40DBF) Posted /CAS by programmable additive latency for Row address: A0 to A12 better command and data bus efficiency Column address: A0 to A9 On-Die-Termination for better signal quality Four internal banks for concurrent operation Programmable RDQS, /RDQS output for making 8 Interface: SSTL 18 organization compatible to 4 organization Burst lengths (BL): 4, 8 /DQS, (/RDQS) can be disabled for single-ended Burst type (BT): Data Strobe operation Sequential (4, 8) Off-Chip Driver (OCD) impedance adjustment is not supported Interleave (4, 8) /CAS Latency (CL): 3, 4, 5, 6, 7 Precharge: auto Precharge option for each burst access Driver strength: normal/weak Low self-refresh current (IDD6) parts are available Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms Average refresh period 7.8s at TC 85C 3.9s at TC 85C Automotive grade 3 compliant with AEC-Q100 grade 3 Automotive grade 2 compliant with AEC-Q100 grade 2 Operating case temperature range TC = 0C to 85C (Commercial) TC = -40C to 95C (Industrial) TC = -40C to 95C (Automotive grade 3) TC = -40C to 105C (Automotive grade 2) Rev. 03 Oct. 13, 2020 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 1/72 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3R12E340DBFF.03 A3R12E30DBF/A3R12E40DBF 512Mb DDR2 SDRAM Ordering Information Organization Internal Speed bin Part number (words bits) Banks (CL-tRCD-tRP) Package Note A3R12E30DBF-AH/AHI/AHB/AHA DDR2-1066 (7-7-7) 64M 8 4 60-ball FBGA A3R12E30DBF-8E/8EI/8EB/8EA DDR2-800 (5-5-5) A3R12E40DBF-AH/AHI/AHB/AHA DDR2-1066 (7-7-7) 32M 16 4 84-ball FBGA A3R12E40DBF-8E/8EI/8EB/8EA DDR2-800 (5-5-5) A3R12E40DBF-8EPH 32M 16 4 DDR2-800 (5-5-5) 84-ball FBGA Low IDD6 A3R12E40DBF-8EJ 32M 16 4 DDR2-800 (5-5-5) 84-ball FBGA A3R12E30DBJ-8EJ 64M 8 4 DDR2-800 (5-5-5) 60-ball FBGA Part Number A 3 R 12 E 4 0D BF - 8E Blank: Commercial normal IDD6 I: Industrial normal IDD6 B: Automotive grade 3 normal IDD6 Option A: Automotive grade 2 normal IDD6 PH: Commercial low IDD6 J Industrial low IDD6 8E: DDR2-800 Speed AH: DDR2-1066 Package Type BF: FBGA Die version 0D: Version 0D 3: x8 IO Configuration 4: x16 Classification E: DDR2 Density 12: 512Mbits Interface R: SSTL-18 Product line 3: DRAM Zentel Product Rev. 03 Oct. 13, 2020 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2/72 2020 Zentel Japan Corporation. All rights reserved.