Product Information

ISL5416KI

ISL5416KI electronic component of Renesas

Datasheet
Up/Down Conv Mixer 1.8V 256-Pin BGA

Manufacturer: Renesas
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90: USD 149.3157 ea
Line Total: USD 13438.41

0 - Global Stock
MOQ: 90  Multiples: 1
Pack Size: 1
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0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 90
Multiples : 1

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ISL5416KI
Renesas

90 : USD 149.3157

     
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DATASHEET ISL5416 FN6006 Rev 3.00 Four-Channel Wideband Programmable DownConverter Aug 2004 The ISL5416 Four-Channel Wideband Programmable Digital Features DownConverter (WPDC) is designed for high dynamic range Up to 95MSPS Input applications such as cellular basestations where the processing of multiple channels is required in a small Four Parallel 16-bit Fixed or 17-bit Floating Point Inputs physical space. The WPDC combines four channels in a Programmable RF Attenuator/VGA Control single package, each including: an NCO, a digital mixer, 32-Bit Programmable Carrier NCO with > 110dB SFDR digital filters, an AGC and a resampling filter. 20-bit Internal Data Path All channels are independently programmable and may be Filter Functions updated in real time. Each of the four channels can select - Multi-Stage Cascaded-Integrator-Comb (CIC) Filter any of the four digital input buses. Each of the tuners can process a W-CDMA channel. Channels may be cascaded or - Two programmable FIR Filters (first up to 32-taps, second up to 64-taps) polyphased for increased bandwidth. Selectable outputs include I samples, Q samples, and AGC gain. Outputs from - Half Band Interpolation Filter the part are available over the parallel, serial or uP - Resampling FIR Filter interfaces. Overall decimation from 1 to >4096 Ordering Information Digital AGC with up to 96dB of Gain Range PART TEMP Up to Four Independent 16-bit Parallel Outputs o NUMBER RANGE ( C) PACKAGE PKG. DWG. Serial Output Option ISL5416KI -40 to 85 256 BGA V256.17x17 ISL5416KIZ -40 to 85 256 BGA V256.17x17 16-bit Parallel P Interface (See Note) (Pb-free) 1.8V core, 3.3V I/O Operation ISL5416EVAL1 25 EVALUATION KIT Evaluation Board and Configuration Software available NOTE: Intersil Pb-free products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free Pb-free available products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Applications Basestation Receivers: GSM/EDGE, CDMA2000, UMTS. Block Diagram TEST REGISTER OUTPUT AOUT(15:8) I AOUT(7:0) INPUT I I I I I AIN(16:0) NCO FIR1 FIR2 SELECT AGC IHBF RESAMPLER FSYNCA ENIA MIXER FILTER CLOCK & FILTER CIC CLKA Q Q Q Q Q OEA Q FORMAT INPUT A CHANNEL O CLKO1 INPUT B CHANNEL 1 CLKO2 INPUT C CHANNEL 2 /INTRPT INPUT D CHANNEL 3 RF ATTENUATOR EOUT(15:0) JTAG SYNCHRONIZATION P INTERFACE VGA CONTROL SYNCO SYNCIN1 SYNCIN2 RESET FN6006 Rev 3.00 Page 1 of 71 Aug 2004 RANGE CONTROL INPUT CHANNEL ROUTING P(15:0) CE ADD(2:0) uP MODE RD or RD/WR WR or DSTRB OUTPUT ROUTING & FORMATTINGISL5416 ISL5416 FN6006 Rev 3.00 Page 2 of 71 Aug 2004 TYPICAL CHANNEL FILTER 24 / CASCADE OUTPUT CASCADE / INPUTS 24 R AIN(16:0) DIGITAL CIC 24 24 24 F 24 24 24 20 20 16 16 16 16 O BIN(16:0) / / / / / / / / / / 16 TUNING FILTER / / GAIN FIR GAIN FIR AGC I RESAMPLING U IHBF 24 24 24 / 24 24 24 20 20 16 16 CIN(16:0) MIXER 16 16 F FILTER 1 2 / / / / / / / / / / N / / DIN(16:0) O D TEST INPUT 1-5 STAGES 1-32 TAPS 1-64 TAPS R=2-64K R=1-8 R=1-8 NCO BYPASS BYPASS BYPASS 32-BIT CONTROL >110 db SFDR CHANNEL 0 TEST CASCADE INPUT A REGISTER IN AOUT(15:0) AIN(16:0) INPUT FORMAT FSYNCA ENIA DIGITAL OUTPUT SLOT CONTROL TUNER FORMAT CH 0, 1 MUXING RANGE OEA CLKA CONTROL EXT AGC CNTRL CASCADE MUX OUT CHANNEL 1 INPUT B AGC GAIN BIN(16:0) BOUT(15:0) INPUT FORMAT ENIB FSYNCB DIGITAL OUTPUT SLOT CONTROL TUNER FORMAT RANGE CH 0, 1 MUXING OEB CLKB CONTROL CHANNEL 2 INPUT C CIN(16:0) INPUT COUT(15:0) FORMAT ENIC DIGITAL OUTPUT SLOT CONTROL FSYNCC TUNER FORMAT RANGE CH 2, 3 MUXING CLKC CONTROL OEC CHANNEL 3 AGC GAIN INPUT D DOUT(15:0) DIN(16:0) INPUT FSYNCD FORMAT ENID DIGITAL OUTPUT SLOT CONTROL TUNER FORMAT RANGE CH 2, 3 MUXING OED CLKD CONTROL MUX CLKO1 SERIAL OUTPUTS EOUT(15:0) CLKO2/ SEQUENCED uP READ DATA TRST INTRPT TMS JTAG SYNCHRONIZATION uP INTERFACE TCLK RESET P(15:0), uPMODE, RD (RD/WR), TDI WR (DSTRB), CE, ADD(2:0) TDO SYNCO SYNCIN1 SYNCIN2 MUX MUX x1, 2, 4, 8 ROUND SATURATE MUX MUX MUX MUX x1, 2, 4, 8 ROUND SATURATE 0 - 96 dB BYPASS MUX O U T P U T M U L T I P L E X I N G SELECT FORMAT TO PARALLEL TO uP TO SERIAL SEQUENCING INTERFACE ROUTING AND ROUTING

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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