74LVC373A Low-Voltage CMOS Octal Transparent Latch With 5 VTolerant Inputs and Outputs (3State, NonInverting) www.onsemi.com The 74LVC373A is a high performance, noninverting octal transparent latch operating from a 1.2 to 3.6 V supply. High impedance MARKING TTL compatible inputs significantly reduce current loading to input DIAGRAM drivers while TTL compatible outputs offer improved switching noise 20 performance. A V specification of 5.5 V allows 74LVC373A inputs I LCX to be safely driven from 5 V devices. TSSOP20 373A 20 The 74LVC373A contains 8 Dtype latches with 3state outputs. DT SUFFIX ALYW CASE 948E When the Latch Enable (LE) input is HIGH, data on the Dn inputs 1 enters the latches. In this condition, the latches are transparent, i.e., a 1 latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D A = Assembly Location inputs a setup time preceding the HIGHtoLOW transition of LE. L, WL = Wafer Lot The 3state standard outputs are controlled by the Output Enable (OE) Y, YY = Year input. When OE is LOW, the standard outputs are enabled. When OE W, WW = Work Week G or = PbFree Package is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. (Note: Microdot may be in either location) Features Designed for 1.2 to 3.6 V V Operation CC ORDERING INFORMATION 5 V Tolerant Interface Capability With 5 V TTL Logic See detailed ordering and shipping information on page 8 of this data sheet. Supports Live Insertion and Withdrawal I Specification Guarantees High Impedance When V = 0 V OFF CC 24 mA Output Sink and Source Capability Near Zero Static Supply Current in all Three Logic States (10 A) Substantially Reduces System Power Requirements ESD Performance: Human Body Model >2000 V Machine Model >200 V These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: September, 2015 Rev. 1 74LVC373A/D74LVC373A 1 OE 11 LE V O7 D7 D6 O6 O5 D5 D4 O4 LE 2 CC LE 3 O0 Q 20 19 18 17 16 15 14 13 12 11 D0 D 5 LE 4 O1 Q D1 D 6 1 2 3 4 567 9 LE 8 10 7 O2 Q D2 D OE O0 D0 D1 O1 O2 D2 D3 O3 GND Figure 1. Pinout (Top View) 9 LE 8 O3 Q D3 D 12 LE 13 O4 Q D4 D PIN NAMES PINS FUNCTION 15 LE OE Output Enable Input 14 O5 Q D5 D LE Latch Enable Input D0D7 Data Inputs 16 LE O0O7 3State Latch Outputs 17 O6 Q D6 D 19 LE O7 18 Q D7 D Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE LE Dn On Operating Mode L H H H Transparent (Latch Disabled) Read Latch L H L L L L h H Latched (Latch Enabled) Read Latch L L l L L L X NC Hold Read Latch H L X Z Hold Disabled Outputs H H H Z Transparent (Latch Disabled) Disabled Outputs H H L Z H L h Z Latched (Latch Enabled) Disabled Outputs H L l Z H = High Voltage Level h = High Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition NC = No Change, State Prior to the Latch Enable HightoLow Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For I Reasons DO NOT FLOAT Inputs CC www.onsemi.com 2