Product Information

74LVT573D,118

Hot 74LVT573D,118 electronic component of Nexperia

Datasheet
NXP Semiconductors Latches 3.3V OCTAL D TRANS

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.3375 ea
Line Total: USD 0.34

1008 - Global Stock
Ships to you between
Fri. 17 May to Thu. 23 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
1008 - WHS 1


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 1
Multiples : 1

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74LVT573D,118
Nexperia

1 : USD 0.3375
10 : USD 0.3361
25 : USD 0.3249
100 : USD 0.292
250 : USD 0.2555
500 : USD 0.251
1000 : USD 0.2485
2000 : USD 0.2435
6000 : USD 0.2435
10000 : USD 0.2435

161 - WHS 2


Ships to you between Thu. 23 May to Mon. 27 May

MOQ : 1
Multiples : 1

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74LVT573D,118
Nexperia

1 : USD 0.6509
10 : USD 0.5485
100 : USD 0.4358
500 : USD 0.3876
1000 : USD 0.3231
2000 : USD 0.2875
4000 : USD 0.2841
10000 : USD 0.2841

1008 - WHS 3


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 34
Multiples : 1

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74LVT573D,118
Nexperia

34 : USD 0.3379
100 : USD 0.3037
250 : USD 0.2657
500 : USD 0.261
1000 : USD 0.2584
2000 : USD 0.2533

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Type
Logic Family
Polarity
Quiescent Current
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Package / Case
Packaging
Brand
Mounting Style
Number Of Channels
Number Of Input Lines
Supply Current - Max
Factory Pack Quantity :
Function
Height
Length
Output Type
Width
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Reset Type
Subcategory
Taric
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74LVT573 3.3 V octal D-type transparent latch 3-state Rev. 9 30 July 2021 Product data sheet 1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits Wide supply voltage range from 2.7 to 3.6 V Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 CNexperia 74LVT573 3.3 V octal D-type transparent latch 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT573D -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVT573PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVT573BQ -40 C to +85 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 C1 1 EN1 1 2 19 1D OE 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 LE mna807 11 mna808 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH 1 2 3 4 5 6 7 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna810 Fig. 3. Logic diagram 74LVT573 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 30 July 2021 2 / 15

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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