Product Information

74LVT74D,118

74LVT74D,118 electronic component of Nexperia

Datasheet
Flip Flop D-Type Pos-Edge 2-Element 14-Pin SO T/R

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

17: USD 0.4133 ea
Line Total: USD 7.03

1723 - Global Stock
Ships to you between
Mon. 13 May to Fri. 17 May
MOQ: 17  Multiples: 1
Pack Size: 1
Availability Price Quantity
1723 - WHS 1


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 1
Multiples : 1

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74LVT74D,118
Nexperia

1 : USD 0.4133

1723 - WHS 2


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 17
Multiples : 1

Stock Image

74LVT74D,118
Nexperia

17 : USD 0.4133

     
Manufacturer
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RoHS - XON
Icon ROHS
Logic Family
Logic Type
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Propagation Delay Time
High Level Output Current
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Technology
Frequency Max
Operating Temp Range
Package Type
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Operating Temperature Classification
Number Of Bits
Clock-Edge Trigger Type
Rad Hardened
Operating Supply Voltage Typ
Operating Supply Voltage Min
Operating Supply Voltage Max
Frequency
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INTEGRATED CIRCUITS 74LVT74 3.3V Dual D-type flip-flop Product specification 1996 Aug 28 IC24 Data Handbook Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 QUICK REFERENCE DATA DESCRIPTION The 74LVT74 is a dual positive edge-triggered D-type flip-flop CONDITIONS featuring individual data, clock, set, and reset inputs also true and SYMBOL PARAMETER T = 25C TYPICAL UNIT amb complementary outputs. Set (SD) and reset (RD) are asynchronous GND = 0V active low inputs and operate independently of the clock input. Propagation When set and reset are inactive (high), data at the D input is t C = 50pF 3.1 PLH L delay ns transferred to the Q and Q outputs on the low-to-high transition of t = 3.3V V 3.6 PHL CC CPn to Qn the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock Input C V = 0V or 3.0V 3 pF IN I triggering occurs at a voltage level and is not directly related to the capacitance transition time of the positive-going pulse. Following the hold time Total supply interval, data at the D input may be changed without affecting the I V = 3.6V 0.5 mA CC CC current levels of the output. PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION RD0 1 14 V CC 2, 12 D0, D1 Data inputs D0 2 13 RD1 3, 11 CP0, CP1 Clock inputs (active rising edge) CP0 3 12 D1 SD0 4 11 CP1 4, 10 SD0, SD1 Set inputs (active LOW) Q0 5 10 SD1 1, 13 RD0, RD1 Reset inputs (active LOW) Q0 6 9 Q1 5, 6, 8, 9 Qn, Qn Data outputs GND 7 8 Q1 SF00045 LOGIC SYMBOL (IEEE/IEC) LOGIC SYMBOL 212 4 & S 5 3 C1 D0 D1 2 1D 3 CP0 6 1 R 4 SD0 1 RD0 10 S 11 CP1 9 11 10 SD1 C2 12 2D 13 RD1 8 13 Q0 Q0Q1 Q1 R V = Pin 14 CC GND = Pin 7 56 98 SA00359 SF00047 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO 40C to +85C 74LVT74 D 74LVT74 D SOT108-1 14-Pin Plastic SSOP 40C to +85C 74LVT74 DB 74LVT74 DB SOT337-1 14-Pin Plastic TSSOP 40C to +85C 74LVT74 PW 74LVT74PW DH SOT402-1 2 1996 Aug 28 853-1872 17244

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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