74LVC162373A 74LVCH162373A 16-bit D-type transparent latch 30 series termination resistors 5 V tolerant inputs/outputs 3-state Rev. 4 14 May 2013 Product data sheet 1. General description The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state outputs for bus-oriented applications. One latch enable (pin nLE) input and one output enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition, the latches are transparent, that is, the latch output changes each time its corresponding data inputs changes. When pin nLE is LOW, the latches store the information that was present at the data inputs a set-up time preceding the HIGH to LOW transition of pin nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. The device is designed with 30 series termination resistors in both HIGH and LOW output stages to reduce line noise. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH162373A only) High-impedance when V =0V CC Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V)74LVC162373A 74LVCH162373A NXP Semiconductors 16-bit D-type transparent latch 30 resistors 5 V tolerance 3-state ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVC162373ADGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm 74LVCH162373ADGG 74LVC162373ADL 40 C to +125 C SSOP48 plastic shrink small outline package 48 leads SOT370-1 body width 7.5 mm 74LVCH162373ADL 4. Functional diagram 1 24 1 1EN 1OE 48 1LE C3 1OE 2OE 24 2EN 2OE 47 1D0 1Q0 2 25 C4 2LE 46 1D1 1Q1 3 47 2 44 1D2 1Q2 5 1D0 1Q0 3D 1 46 3 43 1D3 1Q3 6 1D1 1Q1 5 44 8 41 1D4 1Q4 1D2 1Q2 6 43 40 1D5 1Q5 9 1D3 1Q3 8 41 38 1D6 1Q6 11 1D4 1Q4 40 9 37 1D7 1Q7 12 1D5 1Q5 38 11 36 2D0 2Q0 13 1D6 1Q6 37 12 14 35 2D1 2Q1 1D7 1Q7 36 13 33 2D2 2Q2 16 2D0 4D 2 2Q0 14 35 32 2D3 2Q3 17 2D1 2Q1 33 16 30 2D4 2Q4 19 2D2 2Q2 32 17 29 2D5 2Q5 20 2D3 2Q3 30 19 27 2D6 2Q6 22 2D4 2Q4 29 20 26 2D7 2Q7 23 2D5 2Q5 27 22 1LE 2LE 2D6 2Q6 26 23 2D7 2Q7 mgu768 48 25 mgu770 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC LVCH162373A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 14 May 2013 2 of 18