74LVC1G74DP-Q100H

74LVC1G74-Q100 Single D-type flip-flop with set and reset positive edge trigger Rev. 5 20 September 2021 Product data sheet 1. General description The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package optionsNexperia 74LVC1G74-Q100 Single D-type flip-flop with set and reset positive edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G74DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC1G74DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74LVC1G74GT-Q100 -40 C to +125 C XSON8 plastic extremely thin small outline package SOT833-1 no leads 8 terminals body 1 1.95 0.5 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC1G74DP-Q100 V74 74LVC1G74DC-Q100 V74 74LVC1G74GT-Q100 V74 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram SD SD Q D D Q CP S CP FF C1 Q Q 1D RD R RD 001aah757 001aah758 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Q C C C C C C D Q C C RD SD mna421 CP C C Fig. 3. Logic diagram 74LVC1G74 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 20 September 2021 2 / 16