Product Information

74LVC1G74GT

74LVC1G74GT electronic component of Nexperia

Datasheet
IC, D FLIP-FLOP POS EDGE, XSON8
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.4258 ea
Line Total: USD 2.13

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 5
Multiples : 1

Stock Image

74LVC1G74GT
Nexperia

5 : USD 0.4599
100 : USD 0.2589
500 : USD 0.2099
1000 : USD 0.2021

Read More Specifications

     
Manufacturer
Product Category
Packaging
Flip-Flop Type
Propagation Delay
Supply Voltage Min
Supply Voltage Max
Logic Case Style
No Of Pins
Frequency
Output Current
Trigger Type
Ic Output Type
Operating Temperature Min
Operating Temperature Max
Msl
Svhc
Operating Temperature Range
Supply Voltage Range
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Additional Infomation About Product

74LVC1G74 Single D-type flip-flop with set and reset positive edge trigger Rev. 13 5 December 2016 Product data sheet 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74LVC1G74 NXP Semiconductors Single D-type flip-flop with set and reset positive edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G74DP 40 Cto+125 C TSSOP8 plastic thin shrink small outline package 8 leads body SOT505-2 width 3 mm lead length 0.5 mm 74LVC1G74DC 40 Cto+125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74LVC1G74GT 40 Cto+125 C XSON8 plastic extremely thin small outline package no leads 8 SOT833-1 terminals body 1 1.95 0.5 mm 74LVC1G74GF 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74LVC1G74GD 40 Cto+125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74LVC1G74GM 40 Cto+125 C XQFN8 plastic, extremely thin quad flat package no leads SOT902-2 8 terminals body 1.6 1.6 0.5 mm 74LVC1G74GN 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74LVC1G74GS 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes 1 Type number Marking code 74LVC1G74DP V74 74LVC1G74DC V74 74LVC1G74GT V74 74LVC1G74GF Y4 74LVC1G74GD V74 74LVC1G74GM V74 74LVC1G74GN Y4 74LVC1G74GS Y4 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC1G74 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 13 5 December 2016 2 of 25

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