Product Information

74HCT107D,653

74HCT107D,653 electronic component of Nexperia

Datasheet
Flip Flops DUAL J-K NEG EDGE

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.5739 ea
Line Total: USD 0.57

2404 - Global Stock
Ships to you between
Thu. 09 May to Mon. 13 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2425 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2500
Multiples : 2500

Stock Image

74HCT107D,653
Nexperia

2500 : USD 0.2261
5000 : USD 0.2175
10000 : USD 0.2146
12500 : USD 0.2104
25000 : USD 0.2104
50000 : USD 0.2104

2404 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

Stock Image

74HCT107D,653
Nexperia

1 : USD 0.5739
10 : USD 0.4807
100 : USD 0.3577
500 : USD 0.2955
1000 : USD 0.2369
2500 : USD 0.215
10000 : USD 0.2047
25000 : USD 0.1955

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
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Number Of Input Lines
Number Of Output Lines
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74HC107 74HCT107 Dual JK flip-flop with reset negative-edge trigger Rev. 6 7 July 2021 Product data sheet 1. General description The 74HC107 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: The 74HC107: CMOS levels The 74HCT107: TTL levels ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC107D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT107D 74HC107PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74HC107 74HCT107 Dual JK flip-flop with reset negative-edge trigger 4. Functional diagram 1 1J 3 12 C1 1 1J 1Q 3 4 J Q 1K 2 8 2J 2Q 5 13 FF R 12 1CP CP 9 2CP 8 4 1K 1Q 2 1J 5 K Q 11 2K 9 2Q 6 C1 R 11 1K 6 10 1R 2R R 13 10 aaa-009518 aaa-009519 Fig. 1. Logic symbol Fig. 2. IEC logic symbol C C C C K Q J C C C C R Q C CP 001aab982 C Fig. 3. Logic diagram (one flip-flop) 74HC HCT107 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 7 July 2021 2 / 15

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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