Product Information

74HCT112D,653

74HCT112D,653 electronic component of Nexperia

Datasheet
Flip Flops DUAL J-K NEG EDGE

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.6808 ea
Line Total: USD 0.68

415 - Global Stock
Ships to you between
Tue. 21 May to Thu. 23 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
61 - WHS 1


Ships to you between
Wed. 22 May to Mon. 27 May

MOQ : 1
Multiples : 1

Stock Image

74HCT112D,653
Nexperia

1 : USD 0.4633
10 : USD 0.4009
30 : USD 0.3748
100 : USD 0.3425
500 : USD 0.2921
1000 : USD 0.2841

415 - WHS 2


Ships to you between Tue. 21 May to Thu. 23 May

MOQ : 1
Multiples : 1

Stock Image

74HCT112D,653
Nexperia

1 : USD 0.6808
10 : USD 0.5589
100 : USD 0.4266
500 : USD 0.3806
1000 : USD 0.3001
2500 : USD 0.2162
10000 : USD 0.2116
25000 : USD 0.207
50000 : USD 0.2047

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Number Of Input Lines
Number Of Output Lines
Factory Pack Quantity :
Function
Height
Length
Quiescent Current
Width
Number Of Channels
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Reset Type
Subcategory
Taric
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74HC112 74HCT112 Dual JK flip-flop with set and reset negative-edge trigger Rev. 4 11 January 2021 Product data sheet 1. General description The 74HC112 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits Input levels: For 74HC112: CMOS level For 74HCT112: TTL level Asynchronous set and reset Specified in compliance with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC112D -40 C to +125 C SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 74HCT112D 74HC112PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT112PWNexperia 74HC112 74HCT112 Dual JK flip-flop with set and reset negative-edge trigger 4. Functional diagram 4 10 1SD 2SD SD 3 1J 1Q 5 J Q 11 2J 2Q 9 FF 4 10 1 1CP S S CP 13 2CP 3 11 5 9 1J 1J 1Q 1 13 2 1K 6 C1 C1 6 7 K Q 12 2K 7 2Q 2 12 RD 1K 1K 15 14 1RD 2RD R R 15 14 aaa-024306 aaa-024307 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Q C C C C K Q J C C C C S R C CP C aaa-024308 Fig. 3. Logic diagram (one flip-flop) 5. Pinning information 5.1. Pinning 74HC112 74HCT112 74HC112 1CP 1 16 V CC 74HCT112 1K 2 15 1RD 1J 3 14 2RD 1CP 1 16 V CC 1K 2 15 1RD 4 13 1SD 2CP 1J 3 14 2RD 1Q 5 12 2K 1SD 4 13 2CP 1Q 5 12 2K 1Q 6 11 2J 1Q 6 11 2J 2Q 7 10 2SD 2Q 7 10 2SD GND 8 9 2Q GND 8 9 2Q aaa-024309 aaa-024310 Fig. 4. Pin configuration SOT109-1 (SO16) Fig. 5. Pin configuration SOT403-1 (TSSOP16) 74HC HCT112 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 11 January 2021 2 / 16

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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