HS512K16 HS512K16 8Mb Radiation-Hardened Synchronous Dual-Port SRAM HS512K16 is a high performance synchronous Dual-Port SRAM organized as 524,288 words with 16-bit word. It can be configured as Master or Slave device. Master device can initiate autonomous scrub and demand scrub cycles on Slave device. True dual-port synchronous SRAM, 8Mb memory Selectable between Pipeline and Flow-Through modes Built-in EDAC (Error Detection and Correction) to mitigate soft errors Built-in Scrub Engine for autonomous correction Built-in Address counter for sequential memory access with repeat feature Dual chip enable allows depth and width expansion without additional logic Asynchronous Output Enable for each port Support various clock modes and stress test modes Direct read mode from data bits or parity bits for quick memory testing Cycle Time <20ns flow through mode, <15ns pipeline mode Access time <17ns flow through mode, <12ns pipeline mode Manufactured by TI at DMOS5 wafer fab 130nm CMOS generation with commercial layout rules 5 levels metal, with Cu , Al layers 8T DP SRAM cell CMOS compatible input and output level, three state bidirectional data bus 3.3 +/- 0.3V I/O, 1.5 +/- 0.15V CORE Radiation performance Manufactured by TI with SST 130nm RH process and selective circuit design hardening TID immunity > 300Krads (Si) SER < 1e-10 errors/bit-day geosynchronous orbit & solar minimum (with ECC/Scrub) Latch up immunity > LET = 110 MeV (T=125C) Packaging options: 128pin CQFP, Die Temperature options: -55C to 125C and -55C to 200C page 1 www.voragotech.com Rev 1.1 HS512K16 Figure 1: Block Diagram page 2 www.voragotech.com Rev 1.1