M48Z128 M48Z128Y 5.0 V, 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation unlimited WRITE cycles 10 years of data retention in the absence of power Battery internally isolated until power is first applied 32 Automatic power-fail chip deselect and WRITE 1 protection WRITE protect voltages: (V = power-fail deselect voltage) PFD PMDIP32 module M48Z128: V = 4.75 to 5.5 V CC 4.5 V V 4.75 V PFD M48Z128Y: V = 4.5 to 5.5 V CC 4.2 V V 4.5 V PFD Pin and function compatible with JEDEC standard 128 K x 8 SRAMs RoHS compliant Lead-free second level interconnect September 2011 Doc ID 2426 Rev 6 1/20 This is information on a product still in production but not recommended for new designs. www.st.com 1Contents M48Z128, M48Z128Y Contents 1 Description . 5 2 Operating modes 7 2.1 READ mode 7 2.2 WRITE mode . 9 2.3 Data retention mode . 10 2.4 V noise and negative going transients . 11 CC 3 Maximum ratings . 12 4 DC and AC parameters 13 5 Package mechanical data 16 6 Part numbering 17 7 Environmental information . 18 8 Revision history . 19 2/20 Doc ID 2426 Rev 6