CAT24C44 256-Bit Serial Nonvolatile CMOS Static RAM FEATURES Single 5V Supply JEDEC Standard Pinouts: 8-lead DIP Infinite EEPROM to RAM Recall 8-lead SOIC CMOS and TTL Compatible I/O 100,000 Program/Erase Cycles (EEPROM) Low CMOS Power Consumption: Auto Recall on Power-up Active: 3mA Max. Standby: 30 A Max. Commercial, Industrial and Automotive Temperature Ranges Power Up/Down Protection 10 Year Data Retention DESCRIPTION store protection circuitry prohibits STORE operations The CAT24C44 Serial NVRAM is a 256-bit nonvolatile when VCC is less than 3.5V (typical) ensuring EEPROM memory organized as 16 words x 16 bits. The high data integrity. speed Static RAM array is bit for bit backed up by a nonvolatile EEPROM array which allows for easy trans- The CAT24C44 is manufactured using Catalysts ad- fer of data from RAM array to EEPROM (STORE) and vanced CMOS floating gate technology. It is designed to from EEPROM to RAM (RECALL). STORE operations endure 100,000 program/erase cycles (EEPROM) and are completed in 10ms max. and RECALL operations has a data retention of 10 years. The device is available typically within 1.5 s. The CAT24C44 features unlim- in JEDEC approved 8-lead plastic DIP and SOIC ited RAM write operations either through external RAM packages. writes or internal recalls from EEPROM. Internal false PIN CONFIGURATION PIN FUNCTIONS Pin Name Function DIP Package (L) SOIC Package ( V) SK Serial Clock DI Serial Input 1 8 CE 1 8 V CE V CC CC 2 7 SK 2 7 STORE SK STORE DO Serial Data Output 3 6 DI 3 6 RECALL DI RECALL CE Chip Enable 4 5 DO 4 5 V DO V SS SS RECALL Recall STORE Store V +5V CC V Ground SS 2008 SCILLC. All rights reserved. Doc. No. MD-1083, Rev. T 1 Characteristics subject to change without noticeCAT24C44 BLOCK DIAGRAM EEPROM ARRAY RECALL ROW STATIC RAM STORE DECODE ARRAY STORE CONTROL 256-BIT LOGIC RECALL CE INSTRUCTION COLUMN DI DO REGISTER DECODE SK V CC V SS INSTRUCTION 4-BIT DECODE COUNTER (1)(2) MODE SELECTION Software Write Enable Previous Recall Mode STORESTORESTORESTORESTORE RECALLRECALLRECALLRECALLRECALL Instruction Latch Latch (3) Hardware Recall 1 0 NOP X X Software Recall 1 1 RCL X X (3) Hardware Store 0 1 NOP SET TRUE Software Store 1 1 STO SET TRUE X = Dont Care (4) POWER-UP TIMING Symbol Parameter Min. Max. Units VCCSR V Slew Rate 0.5 0.005 V/m CC t Power-Up to Read Operations 200 s pur t Power-Up to Write or Store Operation 5 ms puw Note: (1) The store operation has priority over all the other operations. (2) The store operation is inhibited when V is below 3.5V. CC (3) NOP designates that the device is not currently executing an instruction. (4) This parameter is tested initially and after a design or process change that affects the parameter. 2008 SCILLC. All rights reserved. 2 Doc. No. MD-1083, Rev. T Characteristics subject to change without notice