X9409 Low Noise/Low Power/2-Wire Bus Data Sheet October 12, 2006 FN8192.4 DESCRIPTION Quad Digitally Controlled Potentiometers (XDCP) The X9409 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS FEATURES integrated microcircuit. Four potentiometers per package The digitally controlled potentiometer is implemented 64 resistor taps using 63 resistive elements in a series array. Between 2-wire serial interface for write, read, and trans- each element are tap points connected to the wiper fer operations of the potentiometer terminal through switches. The position of the wiper on 50 Wiper resistance, typical at 5V. the array is controlled by the user through the 2-wire Four non-volatile data registers for each bus interface. Each potentiometer has associated with potentiometer it a volatile Wiper Counter Register (WCR) and 4 Non-volatile storage of multiple wiper position nonvolatile Data Registers (DR0:DR3) that can be Power-on recall. Loads saved wiper position on directly written to and read by the user. The contents power-up. of the WCR controls the position of the wiper on the Standby current < 1A typical resistor array through the switches. Power-up recalls System V : 2.7V to 5.5V operation CC the contents of DR0 to the WCR. 10k , 2.5k End to end resistance 100 yr. data retention The XDCP can be used as a three-terminal Endurance: 100,000 data changes per bit per potentiometer or as a two-terminal variable resistor in register a wide variety of applications including control, Low power CMOS parameter adjustments, and signal processing. 24 Ld SOIC, 24 Ld TSSOP Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM Pot 0 V CC R R V /R V R R 0 1 H0 HO SS 0 1 Wiper Wiper V /R H2 H2 Resistor Counter Counter Array Register Register Pot 2 V / L0 (WCR) (WCR) R R R R WP 2 3 R 2 3 LO V /R L2 L2 V / W0 SCL V /R R W2 W2 WO SDA Interface and A0 Control A1 8 Circuitry A2 A3 V / W1 Data V /R W3 W3 R W1 R R 0 1 R R Wiper V / 0 1 H1 V /R Wiper H3 H3 Resistor R Counter H1 Resistor Counter Array Register Array Register Pot 1 (WCR) Pot 3 R R (WCR) 2 3 V /R R R L1 L1 2 3 V /R L3 L3 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.X9409 Ordering Information POTENTIOMETER TEMP V LIMITS ORGANIZATION RANGE PKG. CC PART NUMBER PART MARKING (V) (k ) (C) PACKAGE DWG. X9409WS24I-2.7* X9409WS G 2.7 to 5.5 10 -40 to 85 24 Ld SOIC (300 mil) M24.3 X9409WS24IZ-2.7* (Note) X9409WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9409WV24-2.7 X9409WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044 X9409WV24Z-2.7 (Note) X9409WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9409WV24I-2.7* X9409WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9409WV24IZ-2.7* (Note) X9409WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PIN DESCRIPTIONS V /R V /R W0 W0 - W3 W3 The wiper outputs are equivalent to the wiper output of Host Interface Pins a mechanical potentiometer. Serial Clock (SCL) Hardware Write Protect Input (WP) The SCL input is used to clock data into and out of the The WP pin when low prevents nonvolatile writes to X9409. the Data Registers. Serial Data (SDA) PIN NAMES SDA is a bidirectional pin used to transfer data into Symbol Description and out of the device. It is an open drain output and SCL Serial Clock may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires SDA Serial Data the use of a pull-up resistor. For selecting typical A0-A3 Device Address values, refer to the guidelines for calculating typical V /R - V /R , Potentiometer Pin H0 H0 H3 H3 values on the bus pull-up resistors graph. V /R - V /R L0 L0 L3 L3 (terminal equivalent) V /R - V /R Potentiometer Pin W0 W0 W3 W3 Device Address (A - A ) 0 3 (wiper equivalent) The address inputs are used to set the least significant WP Hardware Write Protection 4 bits of the 8-bit slave address. A match in the slave V System Supply Voltage address serial data stream must be made with the CC address input in order to initiate communication with V System Ground (Digital) SS the X9409. A maximum of 16 devices may occupy the NC No Connection 2-wire serial bus. Potentiometer Pins V /R - V /R , V /R - V /R H0 H0 H3 H3 L0 L0 L3 L3 The V /R and V /R inputs are equivalent to the H H L L terminal connections on either end of a mechanical potentiometer. FN8192.4 2 October 12, 2006