X9420 Low Noise/Low Power/SPI Bus Data Sheet April 26, 2006 FN8195.1 DESCRIPTION Single Digitally Controlled (XDCP) Potentiometer The X9420 integrates a single digitally controlled potentiometers (XDCP) on a monolithic CMOS FEATURES integrated microcircuit. Solid-State Potentiometer The digitally controlled potentiometer is implemented SPI Serial Interface using 63 resistive elements in a series array. Between Register Oriented Format each element are tap points connected to the wiper Direct read/write/transfer wiper positions terminal through switches. The position of the wiper on Store as many as four positions per the array is controlled by the user through the SPI bus potentiometer interface. The potentiometer has associated with it a Power Supplies volatile Wiper Counter Register (WCR) and 4 V = 2.7V to 5.5V CC nonvolatile Data Registers (DR0:DR3) that can be V+ = 2.7V to 5.5V directly written to and read by the user. The contents V = -2.7V to -5.5V of the WCR controls the position of the wiper on the Low Power CMOS resistor array through the switches. Power-up recalls Standby current < 1A the contents of DR0 to the WCR. High Reliability Endurance100,000 data changes per bit per The XDCP can be used as a three-terminal register potentiometer or as a two-terminal variable resistor in Register data retention100 years a wide variety of applications including control, 8-bytes of Nonvolatile EEPROM Memory parameter adjustments, and signal processing. 10k or 2.5k Resistor Arrays Resolution: 64 Taps Each Pot 14 Ld TSSOP and 16 Ld SOIC Packages Pb-Free Plus Anneal Available (RoHS Compliant) BLOCK DIAGRAM HOLD R0 R1 V /R CS H H Interface Wiper 8 SCK and Counter Control S0 Register Data Circuitry (WCR) SI V /R R2 R3 L L A0 V /R W W CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. NOT RECOMMENDED FOR NEW DESIGNS POSSIBLE SUBSTITUTE PRODUCT ISL22416, ISL22419, ISL95311, ISL95711X9420 Ordering Information POTENTIOMETER PART ORGANIZATION TEMP. RANGE PKG. PART NUMBER MARKING V LIMITS (V) (k) (C) PACKAGE DWG. CC X9420WS16* X9420WS 5 10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420WS16Z* (Note) X9420WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420WS16I* X9420WS I -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420WS16IZ* (Note) X9420WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420WV14* X9420 W 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420WV14Z* (Note) X9420 WZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420WV14I* X9420 WI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420WV14IZ* (Note) X9420 WZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420YS16* X9420YS 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420YS16Z* (Note) X9420YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YS16I* X9420YS I -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420YS16IZ* (Note) X9420YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YV14* X9420 Y 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420YV14Z* (Note) X9420 YZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420YV14I* X9420 YI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420YV14IZ* (Note) X9420 YZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420WS16-2.7* X9420WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420WS16Z-2.7* (Note) X9420WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420WS16I-2.7* X9420WS G -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420WS16IZ-2.7* X9420WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 (Note) X9420WV14-2.7* X9420 WF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420WV14Z-2.7* (Note) X9420 WZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420WV14I-2.7* X9420 WG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420WV14IZ-2.7* X9420 WZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 (Note) X9420YS16-2.7* X9420YS F 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3 X9420YS16Z-2.7* (Note) X9420YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YS16I-2.7* X9420YS G -40 to +85 16 Ld SOIC (300 mil) M16.3 X9420YS16IZ-2.7* (Note) X9420YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3 X9420YV14-2.7* X9420 YF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9420YV14Z-2.7* (Note) X9420 YZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9420YV14I-2.7* X9420 YG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9420YV14IZ-2.7* (Note) X9420 YZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8195.1 2 April 26, 2006