WRITE CONTROL WRITE FLAGS 3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824 bits IDT72V51433 1,179,648 bits IDT72V51443 2,359,296 bits IDT72V51453 8 bit parallel flag status on both read and write ports FEATURES: Shows PAE and PAF status of 8 Queues Choose from among the following memory density options: Direct or polled operation of flag status bus IDT72V51433 Total Available Memory = 589,824 bits Global Bus Matching - (All Queues have same Input Bus Width IDT72V51443 Total Available Memory = 1,179,648 bits and Output Bus Width) IDT72V51453 Total Available Memory = 2,359,296 bits User Selectable Bus Matching Options: Configurable from 1 to 16 Queues - x18in to x18out 166 MHz High speed operation (6ns cycle time) - x9in to x18out 3.7ns access time - x18in to x9out Queues may be configured at master reset from the pool of - x9in to x9out Total Available Memory in blocks of 512 x 18 or 1,024 x 9 FWFT mode of operation on read port Independent Read and Write access per queue Partial Reset, clears data in single Queue User programmable via serial port Expansion of up to 8 multi-queue devices in parallel is available Default multi-queue device configurations JTAG Functionality (Boundary Scan) -IDT72V51433: 2,048 x 18 x 16Q or 4,096 x 9 x 16Q Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm -IDT72V51443: 4,096 x 18 x 16Q or 8,192 x 9 x 16Q HIGH Performance submicron CMOS technology -IDT72V51453: 8,192 x 18 x 16Q or 16,384 x 9 x 16Q Industrial temperature range (-40C to +85C) is available 100% Bus Utilization, Read and Write on every clock cycle Individual, Active queue flags (OV, FF, PAE, PAF) FUNCTIONAL BLOCK DIAGRAM MULTI-QUEUE FLOW-CONTROL DEVICE Q0 WADEN RADEN FSTR ESTR WRADD RDADD 7 Q1 8 WEN REN WCLK RCLK Q2 OE Q D out in x9, x18 x9, x18 DATA IN DATA OUT OV FF PAF PAE Q15 PAFn 8 PAEn 8 5939 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc JUNE 2003 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 DSC-5939/9 READ FLAGS READ CONTROLIDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES COMMERCIAL AND INDUSTRIAL (16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TEMPERATURE RANGES Bus Matching is available on this device, either port can be 9 bits or 18 bits DESCRIPTION: wide. When Bus Matching is used the device ensures the logical transfer of data The IDT72V51433/72V51443/72V51453 multi-queue flow-control de- throughput in a Little Endian manner. vices are single chip within which anywhere between 1 and 16 discrete FIFO The user has full flexibility configuring queues within the device, being able queues can be setup. All queues within the device have a common data input to program the total number of queues between 1 and 16, the individual queue bus, (write port) and a common data output bus, (read port). Data written into depths being independent of each other. The programmable flag positions are the write port is directed to a respective queue via an internal de-multiplex also user programmable. All programming is done via a dedicated serial port. operation, addressed by the user. Data read from the read port is accessed If the user does not wish to program the multi-queue device, a default option is from a respective queue via an internal multiplex operation, addressed by the available that configures the device in a predetermined manner. user. Data writes and reads can be performed at high speeds up to 166MHz, Both Master Reset and Partial Reset pins are provided on this device. A Master with access times of 3.7ns. Data write and read operations are totally Reset latches in all configuration setup pins and must be performed before independent of each other, a queue maybe selected on the write port and a programming of the device can take place. A Partial Reset will reset the read and different queue on the read port or both ports may select the same queue write pointers of an individual queue, provided that the queue is selected on both simultaneously. the write port and read port at the time of partial reset. The device provides Full flag and Output Valid flag status for the queue A JTAG test port is provided, here the multi-queue flow-control device has a selected for write and read operations respectively. Also a Programmable fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Almost Full and Programmable Almost Empty flag for each queue is provided. Test Access Port and Boundary Scan Architecture. Two 8 bit programmable flag busses are available, providing status of queues See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline not selected for write or read operations. When 8 or less queues are configured of the functional blocks within the device. in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode of bus operation provides the flag busses with all queues status. 2