Product Information

PE42850MLBA-X

PE42850MLBA-X electronic component of pSemi

Datasheet
RF Switch SP5T 30MHz to 1GHz 29dB 32-Pin QFN EP T/R

Manufacturer: pSemi
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

3: USD 26.5494 ea
Line Total: USD 79.65

0 - Global Stock
MOQ: 3  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 3
Multiples : 1
3 : USD 26.5494

     
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Product Specification PE42850 UltraCMOS SP5T RF Switch 301000 MHz Product Description Features The PE42850 is a HaRP technology-enhanced SP5T high power RF switch supporting wireless applications up Dual mode operation: SP5T or SP3T to 1 GHz. It offers maximum power handling of 42.5 dBm HaRP technology enhanced continuous wave (CW). It delivers high linearity and Fast settling time excellent harmonics performance. It has both a standard No gate and phase lag and attenuated RX mode. No blocking capacitors are required if DC voltage is not present on the RF ports. No drift in insertion loss and phase Up to 45 dBm instantaneous power The PE42850 is manufactured on Peregrines in 50 UltraCMOS process, a patented variation of silicon-on- insulator (SOI) technology on a sapphire substrate, Up to 40 dBm instantaneous power offering the performance of GaAs with the economy and < 8:1 VSWR integration of conventional CMOS. 36 dB TX to RX isolation Low harmonics of 2f and 3f = 90 dBc o o (1.15:1 VSWR) Figure 1. Package Type 32-lead 5 5 mm QFN ESD performance 1.5 kV HBM on all pins Figure 2. Functional Diagram of SP3T Figure 3. Functional Diagram of SP5T Configuration Configuration DOC-02178 SP5T, standard configuration ANT can be tied to TX1 and TX2 or TX3 and TX4 Document No. DOC-14614-3 www.psemi.com 2012-2015 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 12 PE42850 Product Specification Table 1. Electrical Specifications 40 to +85 C, V = 2.35.5V, V = 0V or V = 3.45.5V, DD SS EXT DD 1 V = 3.4V (Z = Z = 50 ), unless otherwise noted SS EXT S L Parameter Path Condition Min Typ Max Unit Operating frequency 30 1000 MHz Active TX port 1, 2, 3 or 4 rated power (40 C, +25 C) 30520 MHz 0.25 0.30 dB 5201000 MHz 0.35 0.45 dB 2 Insertion loss ANTTX Active TX port 1, 2, 3 or 4 rated power (+85 C) 30520 MHz 0.30 0.35 dB 5201000 MHz 0.45 0.55 dB Active RX port (40 C, +25 C) 30520 MHz 0.50 0.60 dB 5201000 MHz 0.65 0.80 dB 2 Insertion loss ANTRX Active RX port (+85 C) (un-attenuated state) 30520 MHz 0.60 0.70 dB 5201000 MHz 0.70 0.85 dB 1575 MHz for GPS RX, < 10 dBm, +25 C 1 1.2 dB Active RX port 2 Insertion loss (attenuated state) ANTRX 301000 MHz 15.2 16 16.8 dB 30520 MHz 33 36 dB Isolation (supply biased) TXTX 5201000 MHz 29 30 dB 30520 MHz 34 36 dB Isolation (supply biased) TXRX 5201000 MHz 29 30 dB Unbiased isolation ANTTX +27 dBm 6 dB V , V1, V2, V3 = 0V DD Unbiased isolation ANTRX +27 dBm 14 dB V , V1, V2, V3 = 0V DD Un-attenuated state 30520 MHz 22 27 dB 5201000 MHz 18 22 dB 2 Return loss ANTRX Un-attenuated state, 1575 MHz for GPS RX, < 10 dBm, +25 C 10 14 dB Attenuated state, optimized without attenuator engaged 30520 MHz 16 21 dB 5201000 MHz 13 18 dB 30520 MHz 21 28 dB 2 Return loss ANTTX 5201000 MHz 15 17 dB 30520 MHz +40.0 dBm 2nd and 3rd harmonic TX 521870 MHz +38.5 dBm 90 81 dBc (< 1.15:1 VSWR) 8711000 MHz +37.5 dBm 3 30520 MHz +40.0 dBm (pulsed signal, at 10% duty cycle ) 2nd and 3rd harmonic 3 TX 521870 MHz +38.5 dBm (pulsed signal, at 10% duty cycle ) 82 74 dBc (< 8:1 VSWR) 3 8711000 MHz +37.5 dBm (pulsed signal, at 10% duty cycle ) 2nd and 3rd harmonic 3 TX 301000 MHz +45.0 dBm (pulsed signal, at 10% duty cycle) 80 71 dBc (50 source/load impedance) 2nd and 3rd harmonic TX 301000 MHz +42.5 dBm (CW) 84 75 dBc (50 source/load impedance) 4 Input 0.1dB compression point ANTTX 1000 MHz 45.5 dBm Un-attenuated state 42 dBm IIP3 RX Attenuated state 33 dBm Settling time From 50% control until harmonics within specifications 30 70 s Switching time 50% CTRL to 90% or 10% RF 15 s Notes: 1. In a 2TX1RX SP3T configuration, TX1 and TX2 are tied and TX3 and TX4 are tied respectively. Refer to Application Note AN35 for SP3T performance data. 2. Narrow trace widths are used near each port to improve impedance matching. Refer to evaluation board layouts (Figure 23) and schematic (Figure 24) for details. 3. 10% of 4620 s period. 4. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power P IN. 2012-2015 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-14614-3 UltraCMOS RFIC Solutions Page 2 of 12

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
Peregrine
PEREGRINE SEMICONDUCTOR

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