LS2084AXE7V1B

Document Number LS2084A NXP Semiconductors Rev. 3, 09/2020 Data Sheet: Technical Data LS2084A QorIQ LS2084A/LS2044A Data Sheet Features High-speed peripheral interfaces Four PCIe 3.0 controllers. PCIe3 is capable of 64-bit Arm Cortex-A72 CPUs x8/x4/x2/x1 and SR-IOV and the other three (PCIe1, LS2084A has eight A72 cores arranged as four PCIe2 and PCIe4) are capable of x4/x2/x1 and do clusters. Each cluster has two cores sharing a 1 MB not support SR-IOV. L2 cache At platform speeds of 533 MHz or higher, there is LS2044A has four A72 cores arranged as two no limitation to PCIe speed/width clusters. Each cluster has two cores sharing a 1 MB At platform speed less than 533 MHz, all four PCIe L2 cache controllers can run GEN1 and GEN2 speed at full Up to 2.1 GHz width. For GEN3 speed, PCIe1/PCIe2/PCIe4 can 1 MB platform cache with ECC protection only run x2 width, PCIe3 can only run x4 width. Hierarchical interconnect fabric Additional peripheral interfaces Two serial ATA (SATA 3.0) controllers Two 64-bit DDR4 SDRAM memory controllers with Two high-speed USB 3.0 controllers with integrated ECC and interleaving support PHY Up to 2.1 GT/s Enhanced secure digital host controller DPAA2 (Datapath acceleration architecture, second Serial peripheral interface (SPI) controller generation) incorporating acceleration for the following Quad Serial peripheral interface (QSPI) controller functions: Four I2C controllers Wire-rate IO Processor(WRIOP) for packet parsing, Two DUARTs classification, and distribution Integrated flash controller (IFC 2.0) supporting Queue management for scheduling, packet NAND and NOR flash sequencing, and congestion management Hardware Support for hardware virtualization and partitioning buffer management for buffer allocation and de- enforcement allocation (QBMan) Cryptography acceleration (SEC 5.2) at up to Implements trust architecture combined with 20 Gbps TrustZone RegEx pattern matching acceleration (PME 2.0) at Service processor (SP) provides pre-boot up to 10 Gbps initialization and secure-boot capabilities Decompression/compression acceleration (DCE 1.0) Automotive AEC-Q100 Grade 3 qualified (105C Tj) at up to 20 Gbps Maximum CPU speed 1.8 GHz, maximum DDR qDMA engine data rate 1.8 GT/s 16 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to eight 10 Gbps Ethernet MACs Up to sixteen 1 / 2.5 Gbps Ethernet MACs NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.16 Enhanced secure digital host controller (eSDHC).....................112 2 Pin assignments.................................................................................... 3 3.17 Generic interrupt controller (GIC).............................................116 2.1 1292 ball layout diagrams......................................................... 3 3.18 JTAG controller.........................................................................117 2.2 Pinout list...................................................................................10 3.19 I2C interface.............................................................................. 120 3 Electrical characteristics.......................................................................57 3.20 GPIO interface...........................................................................122 3.1 Overall DC electrical characteristics.........................................57 3.21 Battery-backed security monitor interface................................ 123 3.2 Power sequencing......................................................................62 3.22 High-speed serial interfaces (HSSI).......................................... 124 3.3 Power-down requirements.........................................................64 4 Hardware design considerations...........................................................167 3.4 Power characteristics.................................................................64 4.1 Clock ranges.............................................................................. 167 3.5 Power-on ramp rate................................................................... 67 4.2 Power supply design..................................................................168 3.6 Input clocks............................................................................... 67 5 Thermal................................................................................................ 169 3.7 RESET initialization..................................................................73 5.1 Temperature diode.....................................................................170 3.8 DDR4 SDRAM controller.........................................................73 6 Package information.............................................................................170 3.9 SPI interface.............................................................................. 79 6.1 Package parameters for the FC-PBGA......................................170 3.10 QuadSPI interface......................................................................84 6.2 Mechanical dimensions of the FC-PBGA................................. 170 3.11 DUART interface...................................................................... 88 7 Security fuse processor.........................................................................172 3.12 Ethernet management interface 1 and 2, IEEE Std 1588.......... 89 8 Ordering information............................................................................172 3.13 USB 2.0 interface...................................................................... 92 8.1 Part numbering nomenclature....................................................172 3.14 USB 3.0 interface...................................................................... 93 8.2 Part marking.............................................................................. 173 3.15 Integrated flash controller..........................................................95 9 Revision history....................................................................................174 QorIQ LS2084A/LS2044A Data Sheet, Rev. 3, 09/2020 2 NXP Semiconductors