Product Information

74HC75D,653

Hot 74HC75D,653 electronic component of Nexperia

Datasheet
Latches QUAD BISTABLE LATCH

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

39: USD 0.2897 ea
Line Total: USD 11.3

19400 - Global Stock
Ships to you between
Fri. 03 May to Thu. 09 May
MOQ: 39  Multiples: 1
Pack Size: 1
Availability Price Quantity
4972 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

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74HC75D,653
Nexperia

1 : USD 0.5739
10 : USD 0.437
100 : USD 0.3565
500 : USD 0.3174
1000 : USD 0.2749
2500 : USD 0.2139

3581 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 30
Multiples : 1

Stock Image

74HC75D,653
Nexperia

30 : USD 0.4877
100 : USD 0.4837
250 : USD 0.4794
500 : USD 0.4697

19400 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 39
Multiples : 1

Stock Image

74HC75D,653
Nexperia

39 : USD 0.2897
100 : USD 0.2102
500 : USD 0.206

     
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RoHS - XON
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74HC75 Quad bistable transparant latch Rev. 5 17 March 2021 Product data sheet 1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Complementary Q and Q outputs V and GND on the center pins CC CMOS input levels ESD protection: HBM EIA/JESD22-A114F exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Specified from -40 C to +80 C and from -40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC75D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HC75PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mmNexperia 74HC75 Quad bistable transparant latch 4. Functional diagram 13 C1 16 2 1D 13 1 LE12 15 16 1Q 3 2 1D 1 14 1Q 15 2Q 3 2D 14 2Q 4 C1 L1,2 L3,4 10 3Q 9 6 3D 7 11 1D 3Q 8 9 4Q 7 10 4D 8 4Q 6 11 LE34 4 001aab851 001aab852 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 1D 1Q 2 D Q 16 LE12 1Q 13 CP 1 1D D Q 1Q L1 LE12 CP 1Q LATCH 2D 2Q 1 3 D Q 15 2Q CP 14 2D D Q 2Q L2 CP 2Q LATCH 3D 3Q 2 6 D Q 10 LE34 3Q 4 CP 11 3D D Q 3Q L3 LE34 CP 3Q LATCH 4D 4Q 3 7 D Q 9 4Q CP 8 4D D Q 4Q L4 CP 4Q LATCH 4 001aab853 001aab854 Fig. 3. Functional diagram Fig. 4. Logic diagram 74HC75 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 17 March 2021 2 / 16

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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