Product Information

74HC75N,652

74HC75N,652 electronic component of NXP

Datasheet
Latches QUAD BISTABLE LATCH

Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.3024 ea
Line Total: USD 0.3

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1
Multiples : 1
1 : USD 0.3024
5 : USD 0.2962
50 : USD 0.2839
250 : USD 0.253
1000 : USD 0.2382
2500 : USD 0.2345

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Type
Logic Family
Polarity
Number of Output Lines
High Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Packaging
Package Case
Brand
Mounting Style
Number Of Input Lines
Factory Pack Quantity :
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74HC75 Quad bistable transparant latch Rev. 03 12 November 2004 Product data sheet 1. General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specied in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. 2. Features Complementary Q and Q outputs V and GND on the center pins CC Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Multiple package options Specied from - 40 Cto+80 C and from - 40 C to +125 C.74HC75 Philips Semiconductors Quad bistable transparant latch 3. Quick reference data Table 1: Quick reference data Symbol Parameter Conditions Min Typ Max Unit t , t propagation delay C =15pF PHL PLH L V =5V CC nD to nQ, nQ - 11 - ns LEnn to nQ, nQ - 11 - ns C input capacitance - 3.5 - pF I 1 C power dissipation V = GND to V -42 - pF PD I CC capacitance per latch 1 C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC N = number of inputs switching 2 (C V f ) = sum of outputs. L CC o 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC75N - 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HC75D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HC75DB - 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HC75PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 9397 750 13816 Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 12 November 2004 2 of 20

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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