74HC595S16-13

74HC595 8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER Description Pin Assignments The 74HC595 is an high speed CMOS device. An eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is indepent of all clocks. Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (SHCP). With the output enable (OE asserted low the 3-state outputs Q0-Q7 become active and present th All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register. Features Applications General Purpose Logic Wide Supply Voltage Range from 2.0V to 6.0V Serial to Parallel Data conversion Sinks or sources 8mA at V = 4.5V CC Capture and hold data for extended periods of time. CMOS low power consumption Allow simple serial bit streams from a microcontroller to control as Schmitt Trigger Action at All Inputs many peripheral lines as needed. Inputs accept up to 6.0V Wide array of products such as: ESD Protection Tested per JESD 22 Computer peripherals Appliances Exceeds 200-V Machine Model (A115-A) Industrial control Exceeds 2000-V Human Body Model (A114-A) Exceeds 1000-V Charged Device Model (C101C) Latch-Up Exceeds 250mA per JESD 78, Class II Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See 74HC595 Pin Descriptions Functional Diagram Pin Number Pin Name Function 1 Q1 Parallel Data Output 1 2 Q2 Parallel Data Output 2 3 Q3 Parallel Data Output 3 4 Q4 Parallel Data Output 4 5 Q5 Parallel Data Output 5 6 Q6 Parallel Data Output 6 7 Q7 Parallel Data Output 7 8 GND Ground 9 Q7S Serial Data Output 10 Master Reset Input MR 11 SHCP Shift Register Clock Input 12 STCP Storage Register Clock Input 13 Output Enable Input OE 14 DS Serial Data Input 15 Q0 Parallel Data Output 0 16 Vcc Supply Voltage Logic Diagram 2 of 11 June 2013 74HC595 Diodes Incorporated www.diodes.com Document number: DS35492 Rev. 3 - 2