Product Information

HEF4027BT

HEF4027BT electronic component of Nexperia

Datasheet
4000 Series JK Type 2 3V ~ 15V SOIC-16_150mil RoHS
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.436 ea
Line Total: USD 0.44

327 - Global Stock
Ships to you between
Tue. 28 May to Fri. 31 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
279 - WHS 1


Ships to you between
Tue. 28 May to Fri. 31 May

MOQ : 1
Multiples : 1

Stock Image

HEF4027BT
Nexperia

1 : USD 0.436
10 : USD 0.3769
30 : USD 0.3532
100 : USD 0.3217
500 : USD 0.2072
1000 : USD 0.1994

Read More Specifications

     
Manufacturer
Product Category
Packaging
Brand
Logic Family / Base Number
Flip-Flop Type
Propagation Delay
Frequency
Output Current
Logic Case Style
No. Of Pins
Trigger Type
Ic Output Type
Supply Voltage Min
Supply Voltage Max
Logic Ic Family
Logic Ic Base Number
Operating Temperature Min
Operating Temperature Max
Rohs Phthalates Compliant
Msl
Svhc
Base Number
Ic Generic Number
Logic Function Number
Logic Ic Function
No. Of Gates
Operating Temperature Range
Supply Voltage
Supply Voltage Range
Termination Type
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Additional Infomation About Product

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4027B flip-flops Dual JK flip-flop January 1995 Product specication File under Integrated Circuits, IC04Philips Semiconductors Product specication HEF4027B Dual JK ip-op ip-ops DESCRIPTION FUNCTION TABLES The HEF4027B is a dual JK flip-flop which is INPUTS OUTPUTS edge-triggered and features independent set direct S C CP J K O O D D (S ), clear direct (C ), clock (CP) inputs and outputs D D (O,O). Data is accepted when CP is LOW, and transferred HL X X X H L to the output on the positive-going edge of the clock. The LH X X X L H active HIGH asynchronous clear-direct (C ) and set-direct D HH X X X H H (S ) are independent and override the J, K, and CP inputs. D The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. INPUTS OUTPUTS S C CP J K O O D D n + 1 n + 1 L L L L no change LL H L H L LL L H L H LL H H O O n n Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition O = state after clock positive transition n + 1 PINNING J,K synchronous inputs CP clock input (L to H edge-triggered) S asynchronous set-direct input (active HIGH) D C asynchronous clear-direct input (active HIGH) D O true output O complement output Fig.1 Functional diagram. HEF4027BP(N): 16-lead DIL plastic (SOT38-1) HEF4027BD(F): 16-lead DIL ceramic (cerdip) (SOT74) HEF4027BT(D): 16-lead SO plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, I LIMITS category FLIP-FLOPS DD See Family Specifications Fig.2 Pinning diagram. January 1995 2

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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