Product Information

74HCT259PW,118

74HCT259PW,118 electronic component of Nexperia

Datasheet
NXP Semiconductors Latches 8-BIT ADDRSSBL LATCH

Manufacturer: Nexperia
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Price (USD)

1: USD 0.6313 ea
Line Total: USD 0.63

1636 - Global Stock
Ships to you between
Fri. 10 May to Tue. 14 May
MOQ: 1  Multiples: 1
Pack Size: 1
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Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 2500
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74HCT259PW,118
Nexperia

2500 : USD 0.2233

46 - Global Stock


Ships to you between
Mon. 13 May to Thu. 16 May

MOQ : 1
Multiples : 1

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74HCT259PW,118
Nexperia

1 : USD 1.594
10 : USD 1.3532
30 : USD 1.2211
100 : USD 1.0605
500 : USD 0.9473
1000 : USD 0.918

1636 - Global Stock


Ships to you between Fri. 10 May to Tue. 14 May

MOQ : 1
Multiples : 1

Stock Image

74HCT259PW,118
Nexperia

1 : USD 0.6313
10 : USD 0.5209
100 : USD 0.3956
500 : USD 0.3415
1000 : USD 0.276
2500 : USD 0.2128
10000 : USD 0.2128
25000 : USD 0.2104

     
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74HC259 74HCT259 8-bit addressable latch Rev. 7 2 September 2020 Product data sheet 1. General description The 74HC259 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Input levels: For 74HC259: CMOS level For 74HCT259: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 CNexperia 74HC259 74HCT259 8-bit addressable latch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC259D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT259D 74HC259PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT259PW 74HC259BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT259BQ body 2.5 3.5 0.85 mm 4. Functional diagram 13 Z9 15 G8 14 G10 9,10D DX 4 C10 14 1 0 8R 1 0 LE 5 2 4 0 Q0 G 1 7 3 13 5 6 2 D Q1 2 6 7 Q2 7 3 Q3 9 1 9 A0 4 Q4 2 10 10 A1 Q5 5 3 11 A2 11 Q6 12 6 Q7 12 MR 7 15 mna573 mna572 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Q0 4 1 A0 Q1 5 2 A1 Q2 6 1-of-8 DECODER 3 A2 Q3 7 8 LATCHES Q4 9 14 LE Q5 10 15 MR Q6 11 13 D Q7 12 mna571 Fig. 3. Functional diagram 74HC HCT259 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 7 2 September 2020 2 / 17

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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