Product Information

74HC4017PW-Q100J

74HC4017PW-Q100J electronic component of Nexperia

Datasheet
Counter ICs 74HC4017PW-Q100/TSSOP16/REEL 1
Manufacturer: Nexperia
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1: USD 1.2582 ea
Line Total: USD 1.26

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1

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MOQ : 2500
Multiples : 2500
2500 : USD 0.3699
5000 : USD 0.3489
10000 : USD 0.3373

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Additional Infomation About Product

74HC4017-Q100 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs Rev. 2 1 July 2020 Product data sheet 1. General description The 74HC4017-Q100 74HCT4017-Q100 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC4017-Q100: CMOS level For 74HCT4017-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder jointsNexperia 74HC4017-Q100 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4017D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT4017D-Q100 74HC4017PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HC4017BQ-Q100 -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package no leads 74HCT4017BQ-Q100 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram CP1 13 CP0 14 5-STAGE JOHNSON COUNTER MR 15 Q5-9 DECODING AND OUTPUT CIRCUITRY 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 3 2 4 7 10 1 5 6 9 11 001aah242 Fig. 1. Functional diagram CTRDIV10/DEC 14 3 0 CP1 Q0 3 & 13 13 2 CP0 1 Q1 2 14 15 4 CT = 0 2 Q2 4 7 3 Q3 7 10 4 Q4 10 1 5 Q5 1 5 6 Q6 5 6 7 15 MR Q7 6 9 8 Q8 9 11 9 Q9 11 12 CT5 Q5-9 12 001aah239 001aah240 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC HCT4017 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 1 July 2020 2 / 20

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Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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