Product Information

74AUP2G02GM,125

74AUP2G02GM,125 electronic component of Nexperia

Datasheet
Logic Gates 1.8V DUAL LOW-PWR
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

4000: USD 0.0775 ea
Line Total: USD 310

3880 - Global Stock
Ships to you between
Mon. 13 May to Fri. 17 May
MOQ: 4000  Multiples: 4000
Pack Size: 4000

 More Buying Options & Price Grid(s)

Availability Price Quantity
7760 - WHS 1


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 1
Multiples : 1
1 : USD 0.114
10 : USD 0.1043
25 : USD 0.1021
50 : USD 0.1001
100 : USD 0.1001
1000 : USD 0.1001

3880 - WHS 2


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 4000
Multiples : 4000
4000 : USD 0.0775

7760 - WHS 3


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 84
Multiples : 1
84 : USD 0.1001

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Factory Pack Quantity :
Function
Height
Length
Width
Logic Type
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Subcategory
Taric
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Additional Infomation About Product

74AUP2G02 Low-power dual 2-input NOR gate Rev. 9 27 July 2021 Product data sheet 1. General description The 74AUP2G02 is a dual 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is fully specified for CC partial power down applications using I . The I circuitry disables the output, preventing the OFF OFF potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G02DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AUP2G02GT -40 C to +125 C XSON8 plastic extremely thin small outline package SOT833-1 no leads 8 terminals body 1 1.95 0.5 mm 74AUP2G02GF -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74AUP2G02GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP2G02GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mmNexperia 74AUP2G02 Low-power dual 2-input NOR gate 4. Marking Table 2. Marking codes Type number Marking code 1 74AUP2G02DC p02 74AUP2G02GT p02 74AUP2G02GF pB 74AUP2G02GN pB 74AUP2G02GS pB 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1B B 2A 1 2Y Y 2B A 001aah877 001aah879 mna105 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP2G02 1A 1 8 V CC 1B 2 7 1Y 74AUP2G02 2Y 3 6 2B 1A 1 8 V CC GND 4 5 2A 1B 2 7 1Y 2Y 3 6 2B 001aae472 GND 4 5 2A Transparent top view 001aae412 Fig. 5. Pin configuration SOT833-1, SOT1089, SOT1116 Fig. 4. Pin configuration SOT765-1 (VSSOP8) and SOT1203 (XSON8) 74AUP2G02 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 27 July 2021 2 / 17

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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