74AUP2G08GD

74AUP2G08 Low-power dual 2-input AND gate Rev. 7 18 January 2013 Product data sheet 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1 000 V Low static power consumption; I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP2G08 NXP Semiconductors Low-power dual 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G08DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74AUP2G08GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 1.95 0.5 mm 74AUP2G08GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1089 8 terminals; body 1.35 1 0.5 mm 74AUP2G08GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; body 3 2 0.5 mm 74AUP2G08GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; SOT902-2 8 terminals; body 1.6 1.6 0.5 mm 74AUP2G08GN 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1116 8 terminals; body 1.2 1.0 0.35 mm 74AUP2G08GS 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1203 8 terminals; body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes [1] Type number Marking code 74AUP2G08DC p08 74AUP2G08GT p08 74AUP2G08GF pE 74AUP2G08GD p08 74AUP2G08GM p08 74AUP2G08GN pE 74AUP2G08GS pE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram & 1A 1Y 1B A 2A & 2Y Y 2B B 001aah789 mna221 001aah788 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74AUP2G08 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 18 January 2013 2 of 21