Product Information

74AUP1G86GW-Q100H

74AUP1G86GW-Q100H electronic component of Nexperia

Datasheet
Logic Gates Low-Power 2-Input EXCLUSIVE-OR Gate
Manufacturer: Nexperia
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Price (USD)

1: USD 0.5589 ea
Line Total: USD 0.56

3956 - Global Stock
Ships to you between
Thu. 16 May to Mon. 20 May
MOQ: 1  Multiples: 1
Pack Size: 1

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3751 - WHS 1


Ships to you between Thu. 16 May to Mon. 20 May

MOQ : 1
Multiples : 1
1 : USD 0.4474
10 : USD 0.3197
100 : USD 0.1541
1000 : USD 0.1162
3000 : USD 0.0989
9000 : USD 0.0862
24000 : USD 0.0828
45000 : USD 0.0794
99000 : USD 0.0759

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Additional Infomation About Product

74AUP1G86-Q100 Low-power 2-input EXCLUSIVE-OR gate Rev. 3 21 July 2021 Product data sheet 1. General description The 74AUP1G86-Q100 is a single 2-input EXCLUSIVE-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is CC fully specified for partial power down applications using I . The I circuitry disables the output, OFF OFF preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Low static power consumption I = 0.9 A (maximum) CC Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 Class 3A, exceeds 5000 V HBM JESD22-A114F Class 3A, exceeds 5000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G86GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mmNexperia 74AUP1G86-Q100 Low-power 2-input EXCLUSIVE-OR gate 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G86GW-Q100 pH 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B B Y 1 Y 1 4 = 1 A 4 2 2 A mna038 mna039 mna040 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G86-Q100 B 1 5 V CC A 2 GND 3 4 Y aaa-015062 Fig. 4. Pin configuration SOT353-1 (TSSOP5) 6.2. Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74AUP1G86 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 21 July 2021 2 / 13

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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