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74AUP1G885GN,115

74AUP1G885GN,115 electronic component of Nexperia

Datasheet
NXP Semiconductors Logic Gates 4.6 V 20 mA
Manufacturer: Nexperia
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5000: USD 0.288 ea
Line Total: USD 1440

0 - Global Stock
MOQ: 5000  Multiples: 5000
Pack Size: 5000

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Ships to you between Fri. 10 May to Tue. 14 May

MOQ : 5000
Multiples : 5000
5000 : USD 0.2519
10000 : USD 0.2519
25000 : USD 0.2438

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Additional Infomation About Product

74AUP1G885 Low-power dual function gate Rev. 11 22 July 2019 Product data sheet 1. General description The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A C. The output 2Y provides the Boolean function: 2Y = A B + A C. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP1G885 Low-power dual function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G885DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AUP1G885GT -40 C to +125 C XSON8 plastic extremely thin small outline package SOT833-1 no leads 8 terminals body 1 1.95 0.5 mm 74AUP1G885GF -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74AUP1G885GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP1G885GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74AUP1G885DC pS8 74AUP1G885GT pS8 74AUP1G885GF 58 74AUP1G885GN 58 74AUP1G885GS 58 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A 2Y B 1Y C 001aah898 Fig. 1. Logic diagram 74AUP1G885 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 11 22 July 2019 2 / 18

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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