Product Information

74AUP1G07GW

74AUP1G07GW electronic component of Nexperia

Datasheet
IC, BUFF/DVR, LOW PWR, N INV, TSSOP5
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.6314 ea
Line Total: USD 3.16

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 5
Multiples : 1

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74AUP1G07GW
Nexperia

5 : USD 0.6028
10 : USD 0.4222
100 : USD 0.2511
500 : USD 0.2167
1000 : USD 0.1823
5000 : USD 0.1423

Read More Specifications

     
Manufacturer
Product Category
Packaging
Logic Device Type
Logic Case Style
No Of Pins
Supply Voltage Min
Supply Voltage Max
Operating Temperature Min
Operating Temperature Max
Msl
Svhc
Operating Temperature Range
Supply Voltage Range
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Additional Infomation About Product

74AUP1G07 Low-power buffer with open-drain output Rev. 7 16 July 2012 Product data sheet 1. General description The 74AUP1G07 provides the single non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP1G07 NXP Semiconductors Low-power buffer with open-drain output 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G07GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AUP1G07GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1G07GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP1G07GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1G07GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74AUP1G07GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin SOT1226 small outline package no leads 5 terminals body 0.8 0.8 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP1G07GW pS 74AUP1G07GM pS 74AUP1G07GF pS 74AUP1G07GN pS 74AUP1G07GS pS 74AUP1G07GX pS 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y 2AY 4 2 4 A A Y GND mna623 mna624 mna625 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G07 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 16 July 2012 2 of 19

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