256Mb: x8, x16 Automotive DDR SDRAM Features Automotive DDR SDRAM MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks Features Options Marking V = 2.5V 0.2V, V = 2.5V 0.2V Configuration DD DDQ 1 V = 2.6V 0.1V, V = 2.6V 0.1V (DDR400) 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8 DD DDQ Bidirectional data strobe (DQS) transmitted/ 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16 received with data, that is, source-synchronous data Plastic package OCPL capture (x16 has two one per byte) 66-pin TSOP TG Internal, pipelined double-data-rate (DDR) 66-pin TSOP (Pb-free) P architecture two data accesses per clock cycle Plastic package Differential clock inputs (CK and CK ) 60-ball FBGA (8mm x 12.5mm) CV Commands entered on each positive CK edge 60-ball FBGA (8mm x 12.5mm) CY DQS edge-aligned with data for READs center- (Pb-free) aligned with data for WRITEs Timing cycle time DLL to align DQ and DQS transitions with CK 5ns CL = 3 (DDR400) -5B Four internal banks for concurrent operation Self refresh Data mask (DM) for masking write data Standard None (x16 has two one per byte) Low-power self refresh L Programmable burst lengths (BL): 2, 4, or 8 Temperature rating Auto refresh Industrial (40 C to +85 C) AIT 64ms, 8192-cycle(AIT) Automotive (40 C to +105 C) AAT 16ms, 8192-cycle (AAT) Revision Self refresh (not available on AAT devices) x8, x16 :M Longer-lead TSOP for improved reliability (OCPL) 2.5V I/O (SSTL 2-compatible) Notes: 1. DDR400 devices operating at < DDR333 con- Concurrent auto precharge option supported ditions can use V /V = 2.5V +0.2V. DD DDQ t t t RAS lockout supported ( RAP = RCD) 2. Not all options listed can be combined to AEC-Q100 define an offered product. Use the Part Cata- PPAP submission log Search on www.micron.com for product 8D response time offerings and availability. PDF:09005aef848ea6ef/Source: 09005aef845d3b9c Micron Technology, Inc., reserves the right to change products or specifications without notice. 256mb x8x16 at ddr t66a d1.fm - Rev. A Core DDR Rev. B 11/11 EN 1 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb: x8, x16 Automotive DDR SDRAM Features Table 1: Key Timing Parameters CL = CAS (READ) latency MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B) Clock Rate (MHz) Access DQSDQ Speed Grade CL = 2 CL = 2.5 CL = 3 Data-Out Window Window Skew -5B 133 167 200 1.6ns 0.70ns +0.40ns -6 133 167 n/a 2.1ns 0.70ns +0.40ns 6T 133 167 n/a 2.0ns 0.70ns +0.45ns -75E/-75Z 133 133 n/a 2.5ns 0.75ns +0.50ns -75 100 133 n/a 2.5ns 0.75ns +0.50ns Table 2: Addressing Parameter 32 Meg x 8 16 Meg x 16 Configuration 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks Refresh count 8K 8K Row address 8K (A 12:0 ) 8K (A 12:0 ) Bank address 4 (BA 1:0 ) 4 (BA 1:0 ) Column address 1K (A 9:0 ) 512 (A 8:0 ) Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600(2-2-2) 1 Yes Yes Yes Yes Yes Yes -5B Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes -75E Yes Yes Yes -75Z Yes Yes -75 -5B -6/-6T -75E -75Z -75 -75 Notes: 1. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is V = V = 2.5V 0.2V. DD DDQ PDF:09005aef848ea6ef/Source: 09005aef845d3b9c Micron Technology, Inc., reserves the right to change products or specifications without notice. 256mb x8x16 at ddr t66a d1.fm - Rev. A Core DDR Rev. B 11/11 EN 2 2011 Micron Technology, Inc. All rights reserved.