Product Information

TP2104K1

TP2104K1 electronic component of Microchip

Datasheet
Trans MOSFET P-CH Si 40V 0.16A 3-Pin SOT-23

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

30: USD 5.3928 ea
Line Total: USD 161.78

8876 - Global Stock
Ships to you between
Tue. 21 May to Mon. 27 May
MOQ: 30  Multiples: 1
Pack Size: 1
Availability Price Quantity
8876 - WHS 1


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 30
Multiples : 1

Stock Image

TP2104K1
Microchip

30 : USD 5.35
50 : USD 3.6625
200 : USD 1.1875
300 : USD 0.9175
500 : USD 0.795
750 : USD 0.715

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Id - Continuous Drain Current
Vds - Drain-Source Breakdown Voltage
Rds On - Drain-Source Resistance
Transistor Polarity
Minimum Operating Temperature
Maximum Operating Temperature
Pd - Power Dissipation
Mounting Style
Package / Case
Technology
Number of Channels
Vgs - Gate-Source Voltage
Channel Mode
Configuration
Height
Length
Product
Transistor Type
Width
Brand
Fall Time
Product Type
Rise Time
Factory Pack Quantity :
Subcategory
Typical Turn-Off Delay Time
Typical Turn-On Delay Time
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TP2104 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description This low threshold enhancement-mode (normally-off) High input impedance and high gain transistor utilizes a vertical DMOS structure and Supertexs Low power drive requirement well-proven silicon-gate manufacturing process. This Ease of paralleling combination produces a device with the power handling Low C and fast switching speeds ISS capabilities of bipolar transistors and with the high input Excellent thermal stability impedance and positive temperature coefcient inherent Integral source-drain diode in MOS devices. Characteristic of all MOS structures, Free from secondary breakdown this device is free from thermal runaway and thermally- induced secondary breakdown. Applications Supertexs vertical DMOS FETs are ideally suited to a wide Logic level interfaces - ideal for TTL and CMOS range of switching and amplifying applications where very Solid state relays low threshold voltage, high breakdown voltage, high input Analog switches impedance, low input capacitance, and fast switching Power management speeds are desired. Telecom switches Ordering Information R V Package Options DS(ON) GS(th) BV /BV DSS DGS Device (max) (max) (V) TO-236AB (SOT-23) TO-92 () (V) TP2104 TP2104K1-G TP2104N3-G -40 6.0 -2.0 -G indicates package is RoHS compliant (Green) Pin Conguration DRAIN DRAIN SOURCE SOURC E Absolute Maximum Ratings GATE GATE Parameter Value TO-92 (N3) TO-236AB (SOT-23) (K1) Drain-to-source voltage BV DSS Product Marking Drain-to-gate voltage BV DGS S i T P YY = Year Sealed 2 1 0 4 Gate-to-source voltage 20V WW = Week Sealed Y Y W W = Green Packaging Operating and storage temperature -55C to +150C Package may or may not include the following marks: Si or Soldering temperature* +300C TO-92 (N3) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation W = Code for week sealed of the device at the absolute rating level may affect device reliability. All voltages are P 1 L W referenced to device ground. = Green Packaging * Distance of 1.6mm from case for 10 seconds. Package may or may not include the following marks: Si or TO-236AB (SOT-23) (K1) 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.comTP2104 Thermal Characteristics Power Dissipation I I D D I I O jc ja DR DRM T = 25 C Package (pulsed) (continuous) A O O C/W C/W (mA) (A) (mA) (A) (W) TO-236AB (SOT-23) -160 -0.8 0.36 200 350 -160 -0.8 TO-92 -250 -1.0 0.74 125 170 -250 -1.0 I (continuous) is limited by max rated T . D j Electrical Characteristics (T = 25C unless otherwise specied) A Sym Parameter Min Typ Max Units Conditions BV Drain-to-source breakdown voltage -40 - - V V = 0V, I = -1.0mA DSS GS D V Gate threshold voltage -1.0 - -2.0 V V = V , I = -1.0mA GS(th) GS DS D O V Change in V with temperature - 5.8 6.5 mV/ C V = V , I = -1.0mA GS(th) GS(th) GS DS D I Gate body leakage - -1.0 -100 nA V = 20V, V = 0V GSS GS DS - -10 A V = 0V, V = Max Rating GS DS I Zero gate voltage drain current - DSS V = 0.8 Max Rating, DS - -1.0 mA V = 0V, T = 125C GS A I On-state drain current -0.6 - - A V = -10V, V = -25V D(ON) GS DS - 10 V = -4.5V, I = -50mA Static drain-to-source on-state GS D R - DS(ON) resistance - 6.0 V = -10V, I = -500mA GS D O R Change in R with temperature - 0.55 1.0 %/ C V = -10V, I = -500mA DS(ON) DS(ON) GS D G Forward transconductance 150 200 - mmho V = -25V, I = -500mA FS DS D C Input capacitance - 35 60 ISS V = 0V, GS C Common source output capacitance - 22 30 pF V = -25V, OSS DS f = 1.0 MHz C Reverse transfer capacitance - 8.0 10 RSS t Turn-on delay time - 4.0 6.0 d(ON) V = -25V, DD t Rise time - 4.0 8.0 r ns I = -500mA, D t Turn-off delay time - 5.0 9.0 d(OFF) R = 25 GEN t Fall time - 5.0 8.0 f V Diode forward voltage drop - -1.2 -2.0 V V = 0V, I = -500mA SD GS SD t Reverse recovery time - 400 - ns V = 0V, I = -500mA rr GS SD Notes: O 1. All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V PULS E 10% GENERATOR INPUT -10V R 90% GEN t t (ON) (OFF) D.U.T. t t t t d(ON) r d(OFF) F Outpu t 0V INPU T 90% 90% R L OUTPUT 10% 10% V V DD DD 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2

Tariff Desc

8541.21.00 16 No - - With a dissipation rate of less than 1 W Free

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