2PT5-MAC-SC-UT1

TM ispLever CORECORE 2.5Gbps Ethernet Media Access Controller IP Core Users Guide August 2007 ipug65_01.0 2.5Gbps Ethernet Media Access Controller Lattice Semiconductor IP Core Introduction This document provides technical information about the Lattice 2.5Gbps Ethernet Media Access Controller (2.5Gbps MAC) IP core shown in Figure 1. The 2.5Gbps MAC IP core comes with the following documentation and les: Protected netlist/database Behavioral RTL simulation model Source les for instantiating and evaluating the core The 2.5Gbps MAC IP core evaluation package includes a reference design that is used to instantiate, simulate, map, place and route the core in an example working design. Additional details on this reference design are given in an appendix of this document. The 2.5Gbps MAC IP core supports Lattices IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase of an IP license. It may also be used to evaluate the core in hardware in user-dened designs. Details for using the hardware evaluation capability are described in the Hardware Evaluation section of this document. Features Compliant to IEEE 802.3z standard Generic 8-bit host interface 8-bit wide internal data path Generic transmit and receive FIFO interface Full-duplex operation Transmit and receive statistics vector Programmable Inter Packet Gap (IPG) Multicast address ltering Supports Full-duplex control using PAUSE frames VLAN tagged frames Automatic re-transmission on collision Automatic padding of short frames Multicast and Broadcast frames Optional FCS transmission and reception Optional MII management interface module Supports jumbo frames up to 9600 bytes General Description The 2.5Gbps MAC core can support data rates of 1Gbps or 2.5Gbps in LatticeSC and LatticeSCM devices. The 2.5Gbps MAC transmits and receives data between a host processor and an Ethernet network. The main func- tion of the Ethernet MAC is to ensure that the Media Access rules specied in the 802.3 IEEE standards are met while transmitting and receiving Ethernet frames. Figure 2 shows the frame format of Ethernet packets transmitted and received on the Ethernet network using the 2.5Gbps MAC. The data received from the GMII interface is rst buffered until sufcient data is available to be processed by the Receive MAC (Rx MAC). The Preamble and the Start of Frame Delimiter (SFD) information are then extracted from 2