IS66WV51216EBLL-70BLI

IS66WV51216EALL IS66/67WV51216EBLL OCTOBER 2015 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM DESCRIPTION Features The ISSI IS66WV51216EALL and IS66/67WV51216EBLL are High-Speed access time : high-speed,8M bit static RAMs organized as 512K words by - 70ns ( IS66WV51216EALL ) 16 bits. It is fabricated using ISSIs high performance CMOS - 60ns (IS66/67WV51216EBLL ) technology. CMOS Lower Power Operation This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power Single Power Supply consumption devices. - VDD =1.7V~1.95V( IS66WV51216EALL ) When CS1 is HIGH (deselected) or when CS2 is LOW - VDD =2.5V~3.6V (IS66/67WV51216EBLL ) (deselected), the device assumes a standby mode at which Three State Outputs the power dissipation can be reduced down with CMOS input Data Control for Upper and Lower bytes levels. Lead-free Available Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE ) controls both writing and reading of the memory. A data byte allows Upper Byte (UB ) and Lower Byte (LB ) access. The IS66WV51216 EALL and IS66/67WV51216EBLL are packaged in the JEDEC standard 48-ball mini BGA (6mm x 8mm) and 44-Pin TSOP(TYPE-II). The device is also available for die sales. FUNCTIONAL BLOCK DIAGRAM Address A0~A18 Decode Logic 512K X 16 VDD DRAM Memory Array GND I/O0-I/O7 COLUMN Lower Byte I/O DATA I/O CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 Control OE WE Logic UB LB Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assu mes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specificatio n before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 Rev. B 10/14/2015 www.issi.com - SRAM issi.com IS66WV51216EALL IS66/67WV51216EBLL PIN CONFIGURATIONS 48-Ball miniBGA (6mm x 8mm) Ball Assignment 44-pin TSOP (Type II) 1 2 3 4 5 6 LB OE A0 A1 A2 CS2 A5 44 A A4 1 A6 43 A3 2 42 A7 A2 3 I/Q8 UB A3 A4 CS1 I/Q0 41 B A1 4 OE UB 5 40 A0 39 6 LB CS1 I/Q9 I/Q10 A5 A6 I/Q1 IQ2 C 7 38 I/O15 I/O0 8 37 I/O14 I/O1 9 36 I/O2 I/O13 GND IQ11 A17 A7 I/Q3 VDD D 10 35 I/O12 I/O3 GND 11 34 VDD 33 VDD GND 12 VDD IQ12 NC A16 I/Q4 GND E 32 I/O4 I/O11 13 31 I/O5 14 I/O10 30 15 I/O6 I/O9 I/Q14 I/Q13 A14 A15 I/Q5 I/Q6 F 29 I/O8 I/O7 16 17 28 WE A18 18 27 A16 A8 I/Q15 NC A12 A13 WE I/Q7 G A15 26 A9 19 25 A14 A10 20 24 A13 21 A11 A18 A8 A9 A10 A11 NC H A12 23 22 A17 PIN DESCRIPTIONS Symbol Type Description A0~A18 Input Address Inputs I/Q0~I/Q15 Input / Data Inputs/Outputs Output CS1 , CS2 Input Chip Enable OE Input Output Enable WE Input Write Enable UB Input Upper Byte select LB Input Lower Byte select VDD Power Supply Power GND Power Supply Ground 2 Rev. B 10/14/2015 www.issi.com - SRAM issi.com