IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A FEBRUARY 2012 1Mb x 36 and 2Mb x 18 36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Write a burstable, high-performance, no wait state, device for Internal self-timed write cycle networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, Individual Byte Write Control fabricated with ISSI s advanced CMOS technology. Single R/W (Read/Write) control pin Incorporating a no wait state feature, wait cycles are Clock controlled, registered address, eliminated when the bus switches from read to write, or data and control write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs Interleaved or linear burst sequence control using into a single monolithic circuit. MODE input All synchronous inputs pass through registers are controlled Three chip enables for simple depth expansion by a positive-edge-triggered single clock input. Operations and address pipelining may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal Power Down mode device will hold their previous values. Common data inputs and data outputs All Read, Write and Deselect cycles are initiated by the CKE pin to enable clock and suspend operation ADV input. When the ADV is HIGH the internal burst JEDEC 100-pin TQFP package counter is incremented. New external addresses can be loaded when ADV is LOW. Power supply: Write cycles are internally self-timed and are initiated by NVP: VDD 2.5V ( 5%), VDDQ 2.5V ( 5%) the rising edge of the clock inputs and when WE is LOW. NLP: VDD 3.3V ( 5%), VDDQ 3.3V/2.5V ( 5%) Separate byte enables allow individual bytes to be written. Industrial temperature available A burst mode pin (MODE) defines the order of the burst Lead-free available sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter -200 -166 Units tKQ Clock Access Time 3.1 3.5 ns tKC Cycle Time 5 6 ns Frequency 200 166 MHz Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. B 02/02/2012IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A BLOCK DIAGRAM A2-A19 or A2-A20 x 36: A 0:19 or 1Mx36 ADDRESS x 18: A 0:20 2Mx18 REGISTER MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL OUTPUT WE LOGIC REGISTER BWX (X=a,b,c,d or a,b) BUFFER OE ZZ 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com Rev. B 02/02/2012