CY7C25632KV18
CY7C25652KV18
72-Mbit QDR II+ SRAM Four-Word Burst Architecture
(2.5 Cycle Read Latency) with ODT
72-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
JTAG 1149.1 compatible test access port
Features
Phase-locked loop (PLL) for accurate data placement
Separate independent read and write data ports
Supports concurrent transactions
Configurations
550 MHz clock for high bandwidth
With Read Cycle Latency of 2.5 cycles
Four-word burst for reducing address bus frequency
CY7C25632KV18 4 M 18
Double data rate (DDR) interfaces on both read and write ports
CY7C25652KV18 2 M 36
(data transferred at 1100 MHz) at 550 MHz
Functional Description
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing The CY7C25632KV18 and CY7C25652KV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR II+
SRAM uses rising edges only
architecture. Similar to QDR II architecture, QDR II+ architecture
Echo clocks (CQ and CQ) simplify data capture in high-speed
consists of two separate ports: the read port and the write port to
systems
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
Data valid pin (QVLD) to indicate valid data on the output
dedicated data inputs to support write operations. QDR II+
On-die termination (ODT) feature
architecture has separate data inputs and data outputs to
completely eliminate the need to turn-around the data bus that
Supported for D , BWS , and K/K inputs
[x:0] [x:0]
exists with common I/O devices. Each port is accessed through
Single multiplexed address input bus latches address inputs
a common address bus. Addresses for read and write addresses
for read and write ports
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
Separate port selects for depth expansion
independent of one another. To maximize data throughput, both
Synchronous internally self-timed writes
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 18-bit words
QDR II+ operates with 2.5 cycle read latency when DOFF is
(CY7C25632KV18), or 36-bit words (CY7C25652KV18) that
asserted HIGH
burst sequentially into or out of the device. Because data is
Operates similar to QDR I device with 1 cycle read latency when transferred into and out of the device on every rising edge of both
DOFF is asserted LOW input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus turn-arounds.
Available in 18, and 36 configurations
These devices have an On-Die Termination feature supported
Full data coherency, providing most current data
for D , BWS , and K/K inputs, which helps eliminate
[x:0] [x:0]
[1] external termination resistors, reduce cost, reduce board area,
Core V = 1.8 V 0.1 V; I/O V = 1.4 V to V
DD DDQ DD
and simplify board routing.
Supports both 1.5 V and 1.8 V I/O supply
Depth expansion is accomplished with port selects, which
HSTL inputs and variable drive HSTL output buffers
enables each port to operate independently.
Available in 165-ball FBGA package (13 15 1.4 mm)
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
Offered in both Pb-free and non Pb-free packages
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description 550 MHz 500 MHz 450 MHz 400 MHz Unit
Maximum Operating Frequency 550 500 450 400 MHz
Maximum Operating Current 18 920 850 780 710 mA
36 1310 1210 1100 1000
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V .
DDQ DD
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-66482 Rev. *E Revised May 9, 20141M x 18 Array 512K x 36 Array
1M x 18 Array 512K x 36 Array
1M x 18 Array 512K x 36 Array
1M x 18 Array 512K x 36 Array
CY7C25632KV18
CY7C25652KV18
Logic Block Diagram CY7C25632KV18
18
D
[17:0]
Write Write Write Write
20
Address
A
Reg Reg Reg Reg
(19:0)
Register
20 Address
A
(19:0)
Register
K RPS
Control
CLK
K
Logic
Gen.
DOFF
Read Data Reg.
CQ
72
V
36
REF
18 CQ
Reg. Reg.
Control
WPS 18
Logic
18
18
36
BWS Q
Reg.
[1:0] [17:0]
18
QVLD
Logic Block Diagram CY7C25652KV18
36
D
[35:0]
Write Write Write Write
19
Address
A
Reg Reg Reg Reg
(18:0)
Register
19 Address
A
(18:0)
Register
RPS
K
Control
CLK
K
Logic
Gen.
DOFF Read Data Reg.
CQ
144
V
72
REF
CQ
36
Reg.
Reg.
Control
WPS 36
Logic
36
72 36
Q
BWS
Reg.
[3:0] [35:0]
36
QVLD
Document Number: 001-66482 Rev. *E Page 2 of 32
Write Add. Decode Write Add. Decode
Read Add. Decode Read Add. Decode