CY7C1062G CY7C1062GE 16-Mbit (512 K words 32 bits) Static RAM with Error-Correcting Code (ECC) 16-Mbit (512 K words 32 bits) Static RAM with Error-Correcting Code (ECC) Features Functional Description High speed CY7C1062G and CY7C1062GE are high-performance CMOS fast static RAM devices with embedded ECC. Both have three t = 10 ns/15 ns AA chip enables, giving easy memory expansion features. The Embedded error-correcting code (ECC) for single-bit error CY7C1062GE device includes an error indication pin that signals correction the host processor in the case of a single bit error-detection and Low active and standby current correction event. I = 90 mA typical CC To write to the device, take Chip Enables (CE , CE , and CE 1 2 3 I = 20 mA typical SB2 LOW) and Write Enable (WE) input LOW. If Byte Enable A (B ) A Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V is LOW, then data from I/O pins (I/O through I/O ) is written into 0 7 the location specified on the address pins (A through A ). If 0 18 1.0-V data retention Byte Enable B (B ) is LOW, then data from I/O pins (I/O through B 8 Automatic power-down when deselected I/O ) is written into the location specified on the address pins 15 (A through A ). Likewise, B and B correspond with the I/O 0 18 C D Transistor-transistor logic (TTL) compatible inputs and outputs pins I/O to I/O and I/O to I/O , respectively. 16 23 24 31 ERR pin to indicate 1-bit error detection and correction , CE , and CE To read from the device, take Chip Enables (CE 1 2 3 Available in Pb-free 119-ball plastic ball grid array (PBGA) LOW) and Output Enable (OE) LOW while forcing the Write package Enable (WE) HIGH. If the first B is LOW, then data from the A memory location specified by the address pins appear on I/O to 0 I/O . If B is LOW, then data from memory appears on I/O to 7 B 8 I/O . Likewise, B and B correspond to the third and fourth 15 C D bytes. See Truth Table CY7C1062G/CY7C1062GE on page 15 for a complete description of read and write modes. The input and output pins (I/O through I/O ) are placed in a 0 31 high-impedance state when the device is deselected (CE , CE , 1 2 or CE HIGH), the outputs are disabled (OE HIGH), the byte 3 selects are disabled (B HIGH), or during a write operation A-D (CE CE and CE LOW and WE LOW). 1, 2 3 On the CY7C1062GE device, the detection and correction of a single-bit error in the accessed location is indicated by the 1 assertion of the ERR output (ERR = High) . CY7C1062G and CY7C1062GE devices are available in Pb-free 119-ball plastic ball grid array (PBGA) package. For a complete list of related documentation, click here. Note 1. This device does not support automatic write-back on error detection. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-81609 Rev. *G Revised November 30, 2017CY7C1062G CY7C1062GE Logic Block Diagram CY7C1062G I/O I/O ECCENCODER DATA DRIVERS 0 7 IN I/O I/O 8 15 I/O I/O 16 23 I/O I/O 24 32 WE B D B C A0 B B A1 B A A2 512Kx32 A3 RAMARRAY A4 A5 A6 A7 A8 A9 COLUMNDECODER CE 3 WE CE 2 CE 1 OE B B B B D C B A Logic Block Diagram CY7C1062GE I/O I/O ECCENCODER DATA DRIVERS 0 7 IN I/O I/O 8 15 I/O I/O 16 23 I/O I/O 24 32 WE B D B C A0 B B A1 B A A2 512Kx32 A3 ERR RAMARRAY A4 A5 A6 A7 A8 A9 COLUMNDECODER CE WE 3 CE2 CE 1 OE B B B B D C B A Document Number: 001-81609 Rev. *G Page 2 of 20 ROWDECODER ROWDECODER A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 A18 A18 SENSEAMPLIFIERS SENSEAMPLIFIERS ECCDECODER ECCDECODER