INCH POUND MIL-M-38510/289A 23 JANUARY 2006 SUPERSEDING MIL-M-38510/289 4 DECEMBER 1986 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, CMOS 4096 BIT STATIC RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON Inactive for new desi gn after 24 July 1995. This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF-38535. 1. SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, CMOS static, 4096-bit random access memories. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device type. The device type is as follows: Device type Circuit organization Address access time 01, 03 4096 words / 1-bit t = 35 ns, 55 ns AVQV (T = -55C instant-on C to +125C) 1/ 02, 04 1024 words / 4-bit t = 35 ns, 55 ns AVQV (T = -55C instant-on C to +125C) 1/ 1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535. 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18, CDIP2-T18 18 Dual in line package X See figure 1 18 flat package Y GDFP2-F18 18 flat package 3 CQCC3-N18 18 Rectangular leadless chip carrier 1/ T = T at test time equals zero. Instant-on is defined as all functional characteristics guaranteed at all C A temperatures 50 ms after power is applied. Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to bipolar dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at MIL-M-38510/289A 1.3 Absolute maximum ratings. Voltage on any pin with respect to ground 2/ .................. -0.5 V dc to +7.0 V Storage temperature range ............................................ -65C to +150C Power dissipation (P ) ................................................. 1.0 mW D Lead temperature (soldering, 5 seconds) ....................... +270C Maximum junction temperature (T ) 3/ ........................... +150C J Thermal resistance, junction-to-case ( ) .................. JC Cases V, Y and 3 (See MIL-STD-1835) Case X..................................................................... 55C/W 4/ Maximum dc output current............................................. 20 mA 1.4 Recommended operating conditions. Supply voltage range (V -V ) ...................................... 4.5 V dc to 5.5 V dc CC SS High level input voltage (V ) (all inputs).......................... 2.0 V dc to 6.0 V dc (device 01, 02) IH High level input voltage (V ) (all inputs).......................... 2.0 V dc to V (device 03, 04) IH CC Low level input voltage (V ) (all inputs)........................... -3.0 V dc to +0.8 V dc IL Operating case temperature (T ).................................... -55C to +125C C Device Device Device Operating DeviceType 01 Type 02 Type 03 Type 04 Condition Min Max Units Min Max Units Min Max Units Min Max Units Read Cycle 35 ns 35 ns 55 ns 55 ns Time (t ) AVAV Address access time (t ) 35 ns 35 ns 55 ns 55 ns AVQV 65 Chip select access time (t ) 35 ns 35 ns 55 ns ns ELQV 8/ Output hold time from address change 5 ns 0 ns 5 ns 5 ns (t ) AVQX Chip select to output in low Z (t ) 5/ 6/ 5 ns 10 ns 5 ns 10 ns ELQL Chip deselect to output in high Z (t ) EHQZ 0 30 ns 0 20 ns 0 30 ns 0 20 ns 5/ 6/ Chip select to power up time (t ) 0 ns 0 ns 0 ns 0 ns ELPU Chip deselect to power down time (t ) 20 ns 30 ns 20 ns 30 ns EHPD Write cycle time (t ) 35 ns 35 ns 55 ns 55 ns AVAV Pulse width, chip select to end of write 35 ns 30 ns 45 ns 50 ns (t ) 7/ ELWH Address valid to end of write (t ) 35 ns 30 ns 45 ns 50 ns AVWH Pulse width, write (t ) 20 ns 30 ns 25 ns 40 ns WLWH Data valid to end of write (t ) 20 ns 20 ns 25 ns 20 ns DVWH Address set up to write start (t ) 0 ns 0 ns 0 ns 0 ns AVWL Write recovery time (t ) 0 ns 5 ns 10 ns 5 ns WHAX Data hold from write end (t ) 10 ns 0 ns 10 ns 0 ns WHDX Write enabled to output in high Z (t ) WLQZ 0 20 ns 0 10 ns 0 25 ns 0 20 ns 6/ Output active from end of write (t ) 6/ WHQX 0 ns 0 ns 0 ns 0 ns 7/ 2/ Under absolute maximum ratings, the voltage values are with respect to the most negative supply voltage, V . Throughout the remainder of this specification, the voltage values are with respect to V . SS SS 3/ Maximum junction temperature (T ) may be increased to 175C during the burn in and steady state life test. J 4/ When a thermal resistance value is included in MIL-STD-1835, it will supersede the value stated herein. 5/ At any given temperature and voltage condition, t maximum is less than t minimum both for a ELQL EHQZ given device and from device to device. 6/ Tansition is measured 500 mV from steady state voltage with specified loading. 7/ The internal write time of the memory is defined by the overlap of CS low and WE low. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 8/ Chip deselected less than 55 ns prior to selection. 2