The Router 5000 chip is used to build Router 5000 high performance half-routers that Model increase the scalability and surviveability 14315R-100 of LONWORKS control networks and lower installation costs by allowing mixed physcial media to be used in a single installation. Based on the Neuron 5000 core, the Router 5000 provides the design flexibility to interface to the external transceiver of your choice for building a LONWORKS communication channel. FEATURES 3.3V operation. transceiver types. Commonly used forwards all valid packets that match its transceiver types include support for domains, whereas a Repeater forwards Higher Performance TP/FT-10, TP-RS485, TP/XF-78F, all valid packets. Configured routers Clock rate up to 40 MHz TP/XF-1250 channel types and the are easily installed using an installation Larger buffer size to allow for LPT-11 transceiver. These external tool that calculates network topology extended NVs and improved transceivers can run at interface bit and layer 4 timing parameters, such throughput. rates from 9.8 kbps to 1.25 Mbps. as the LonMaker Integration Tool or Transceiver-independent design. an installation tool based on the LNS The Router parameters can be stored in Compact 7mm x 7mm 48-pin network operating system. an external EEPROM with a maximum QFN package. size of 2 KB. Customers will need to Usage Can be connected to a transceiver specify router parameters that are A half-router consists of the Router 5000 running at any Lno Wskro bit rate applicable for the external transceiver chip and an external transceiver along from 610 bps to 1.25Mbps. type used with the Router 5000. For a with a crystal to generate the clock and Logical Isolation between two full router design, customers can use an external memory to hold the router half-routers improves system the same crystal and the same power table. Any type of external transceiver reliability by isolating failures supply to implement the clock and power can be used with the Router 5000, between channels. supply needed for the two half-routers, such as a TP/FT-10, TP-RS485, TP/XF- which helps minimize the overall size 78, TP/XF-1250 or LPT-11 transceiver. Transparent multi-channel and needed to implement a full router. The Router 5000 is compatible with all multi-media support. Lno Wskro transceivers, including standard A Router 5000 can use one of four -40C to +85C operating transceivers for free topology, link power, routing algorithms: Congfi ured router, temperature range. twisted pair, and power line. Using Learning router, Bridge or Repeater. multiple communications media can The ability to choose these options minimize installation costs and increase The Router 5000 includes the Router allows the customer to trade off system system performance by allowing easily rfi mware required to implement a performance for ease of installation. installed media, such as power line or half-router. Its compact form factor Configured and Learning routers fall into link power, to be combined with media minimizes the space required to develop a class of routers known as intelligent such as TP/XF-1250 twisted pair. The two a half-router. Customers can develop routers, which use routing tables to half-routers of a full router are logically two half-routers to build a full router selectively forward messages based isolated so that a failure in one half-router with the same or different external on the destination address. A Bridge will not affect the other. 1Router 5000 Pin Congfi uration Pin Pin Type Description Name Number Digital JTAG Test TMS 20 Input Mode Select GND PAD Digital JTAG Test TDI 21 Input Data In SVC~ 1 36 GND IO0 2 35 NC Digital JTAG Test TDO 22 IO1 3 34 CP1 Output Data Out IO2 4 33 AGND Oscillator Crystal oscillator IO3 5 32 CP0 XIN 23 In Input VDD1V8 6 31 AVDD3V3 IO4 7 30 VDD3V3 Oscillator Crystal oscillator XOUT 24 VDD3V3 8 29 VIN3V3 Router 5000 Out Output IO5 9 28 RST~ IO6 10 27 VOUT1V8 1.8 V Power Input IO7 11 26 GNDPLL VDDPLL 25 Power (from internal IO8 12 25 VDDPLL voltage regulator) GNDPLL 26 Power Ground 1.8 V Power VOUT1V8 27 Power Output (of internal Dashed line represents Pad (pin 49) voltage regulator) Pad must be connected to GND RST~ 28 Digital I/O Reset (active low) Figure 2: Router 5000 Pinout VIN3V3 29 Power 3.3 V Power Input VDD3V3 30 Power 3.3 V Power Router 5000 Chip Pin Assignments AVDD3V3 31 Power 3.3 V Power Pin Pin Type Description Communi- CP0: Receive Name Number CP0 32 cations serial data Service SVC~ 1 Digital I/O AGND 33 Ground Ground (active low) Communi- CP1: Transmit IO0 CP1 34 IO0 2 Digital I/O cations serial data Figure 1: Block Diagram of a LONWORKS Router (side A to side B) Based on the Router 5000 NC 35 N/A Do Not Connect IO1 IO1 3 Digital I/O GND 36 Ground Ground (side A to side B) Lno Wskro application programs do not CP2: External IO2 Communi- IO2 4 Digital I/O have to be modified to work with routers. CP2 37 transceiver (side A to side B) cations enable output Only the network configuration of a IO3 IO3 5 Digital I/O Communi- CP3: Do Not (side A to side B) device has to be modified when a device CP3 38 cations Connect 1.8 V Power Input is moved to the far side of a router. The Communi- CP4: Collision VDD1V8 6 Power (from internal required modicfi ations to the network CP4 39 cations detect input voltage regulator) configuration can be done automatically SPI slave select 0 IO4 CS0~ 40 Digital I/O IO4 7 Digital I/O by an installation tool. (active low) (side A to side B) VDD3V3 41 Power 3.3 V Power VDD3V3 8 Power 3.3 V Power Routers are also independent of VDD3V3 42 Power 3.3 V Power IO5 the network variables and message IO5 9 Digital I/O 2 (side A to side B) I C: serial data (SDA) tags in a system, and can forward an Digital I/O IO6 SDA CS1~ 43 unlimited number of them, which saves SPI: slave select 1 IO6 10 Digital I/O for Memory (side A to side B) (active low) development cost because no code IO7 1.8 V Power Input IO7 11 Digital I/O development is required to use routers (side A to side B) VDD1V8 44 Power (from internal in a system. It also saves installation IO8 voltage regulator) IO8 12 Digital I/O and maintenance costs because router (side A to side B) Digital I/O 2 SCL 45 I C: serial clock configuration is automatically managed IO9 for Memory IO9 13 Digital I/O (side A to side B) by network server tools based on Digital I/O SPI master input, MISO 46 IO10 for Memory slave output (MISO) LNS Server. Monitoring and Control IO10 14 Digital I/O (side A to side B) Digital I/O Applications, such as those based on the SCK 47 SPI serial clock IO11 for Memory LCA Object Server OCX, do not require IO11 15 Digital I/O (not used for Digital I/O SPI master output, modicfi ations to work with multi-channel MOSI 48 routers) for Memory slave input (MOSI) networks when routers are used. All 1.8 V Power Input PAD 49 Ground Pad Ground VDD1V8 16 Power (from internal network configuration is performed voltage regulator) Table 1: Router 5000 Chip Pin Description over the installed network, further Digital JTAG Test Reset minimizing installation and maintenance TRST~ 17 Input (active low) costs because routers do not have to VDD3V3 18 Power 3.3 V Power be physically accessed to change their Digital TCK 19 JTAG Test Clock configuration. Input 2 IO9 13 48 MOSI IO10 14 47 SCK IO11 15 46 MISO VDD1V8 16 45 SCL TRST~ 17 44 VDD1V8 VDD3V3 18 43 SDA CS1~ TCK 19 42 VDD3V3 TMS 20 41 VDD3V3 TDI 21 40 CS0~ TDO 22 39 CP4 XIN 23 38 CP3 XOUT 24 37 CP2