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BT656 TPG BT.656 Test Pattern Generator Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Test patterns generated as an industry standard 8-bit ITU-R BT.656 stream YCbCr 4:2:2 output pixels Both PAL and NTSC (720 x 576i and 720 x 480i) formats supported Choice of 6 different test pattern outputs All signals synchronous with the pixel clock Compatible with a wide range of video codec ICs Tiny implementation size makes the core suitable for even the smallest FPGAs and CPLDs Applications Figure 1: BT.656 Test pattern generator Digital video testing and prototyping General Description Default output displays and simple screen savers The BT656 TPG module (Figure 1) is a versatile test pattern generator capable of producing a range of test patterns in 8-bit ITU-R BT.656 format. The module is ideal for use in the prototyping stages of digital Generic Parameters video systems, or as a known good reference source for BT.656 video. The video mode and output test pattern is controlled by a pair of generic Generic name Description Type Valid Range parameters. The video output mode can be set using the parameter tpg mode. This gives the option of either 576i (PAL) or 480i (NTSC) tpg mode Output video mode integer 0: PAL (576i) output formats. The type of test pattern output is controlled by the 1: NTSC (480i) tpg type parameter. In total there are a range of 6 different test patterns to choose from. tpg type Test pattern type integer 0 : colour bars 1 : colour checks The output video is a standard BT.656 8-bit stream that is synchronous 2 : hatch with the clk signal. The clock frequency is normally set to 27 MHz in 3 : crosses order to comply with the BT.656 standard and the 16-bit pixel sample rate 4 : blue screen of 13.5 MHz. 5 : alternating fields Test pattern mode and type Pin-out Description By modifying the test pattern type, the colour and appearance of the test pattern may be controlled. Figure 2 on the following page gives a 1 description of each pattern available . Pin name I/O Description Active state The images show the consecutive odd and even fields and also include clk in Pixel clock rising edge the video blanking regions. The vertical blue lines are where the EAV and (normally 27 MHz) SAV codes are positioned in the video stream. reset in Asynchronous reset low video out 7:0 out BT.656 output video (8-bit) data video val out BT.656 output video valid high 1 Original bitmap images for the output test patterns may be provided on request. Other custom test patterns can also be provided. Please contact Zipcores for more information. Copyright 2014 www.zipcores.com Download this VHDL Core Page 1 of 3BT656 TPG BT.656 Test Pattern Generator Rev. 1.2 Functional Timing An example output waveform is shown in Figure 3 below. The 8-bit output data is valid on the rising clock-edge of clk when video val is high. The video val signal is active high with the first valid byte of the stream after a system reset. Figure 3: BT.656 output video timing Source File Description All source files are provided as text files coded in VHDL. The following table gives a brief explanation of each file. Source file Description bt 656 tpg enc.vhd Main BT.656 encoder module bt 656 tpg unpack.vhd 32-bit to 8-bit unpacker bt 656 tpg.vhd Top-level component bt 656 tpg bench.vhd Top-level testbench Functional Testing An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: 1. bt 656 tpg enc.vhd 2. bt 656 tpg unpack.vhd 3. bt 656 tpg.vhd 4. bt 656 tpg bench.vhd The VHDL testbench instantiates the BT 656 TPG component with the video format set to 576i (PAL) and the output test pattern set to colour bars. The simulation must be run for at least 20 ms during which time the outputs are captured to a text file called bt 656 out.txt. This file contains the captured BT.656 stream with each byte on a consecutive line. Synthesis and Implementation Figure 2: Video output test patterns for 576i and 480i video The files required for synthesis and the design hierarchy is shown below: bt 656 tpg.vhd bt 656 tpg enc.vhd bt 656 tpg unpack.vhd Copyright 2014 www.zipcores.com Download this VHDL Core Page 2 of 3