CODEC 8B10B 8b/10b Encoder/Decoder Rev. 1.2 Key Design Features Block Diagram Technology independent soft IP Core for FPGA, ASIC and SoC devices reset Supplied as human readable VHDL (or Verilog) source code Separate Encoder/Decoder pair that implements the standard IBM 8b/10b line code for a DC-balanced serial data stream ENC 0 Fully synchronous design with data input and output valid flags nb x 8 nb x 10 Encoder and Decoder have a latency of 1 clock cycle datain dataout Generic parallel input and output data widths nb nb datain k dataout kerr (specified in whole numbers of input and output bytes) ENC 1 Supports all standard control bytes - K.28.0 to K.30.7 datain val dataout val Error flags indicate control byte errors and general decoding errors dataout rd Running Disparity (RD) calculations handled internally and encoder also provides current RD as an output for downstream devices ENC N clk Fully scalable, generic architecture (a) Suitable for use in serial data links of 6 GHz+ on basic FPGA 1 ENC 8B10B N devices reset Applications High speed serial interfaces with embedded clocking Transmission of DC-balanced, AC-coupled serial data DEC 0 Prerequisite for the transmission of serial data over large nw x 10 nw x 8 distances datain dataout Ideal for use in generic serial links (e.g. LVDS or any differential nw electrical standard) dataout k datain val DEC 1 Encoding scheme used in a wide range of communication nw systems such as Ethernet, PCI Express, DVB-ASI, Digital dataout kerr Audio, Fibre Channel, etc. dataout val Generic Parameters DEC N Generic name Description Type Valid range clk nb (encoder) Number of bytes to integer 1 (b) encode in parallel DEC 8B10B N nw (decoder) Number of 10-bit integer 1 words to decode in Figure 1: Figure 1: Simplified architectures for the: parallel (a) 8b/10b Encoder and (b) 8b/10b Decoder modules 1 Xilinx 7-series used as a reference Copyright 2020 www.zipcores.com Download this IP Core Page 1 of 4CODEC 8B10B 8b/10b Encoder/Decoder Rev. 1.2 The design is comprised of an independent encoder and decoder module Pin-out Description (Figure 1) that may be used separately or together as a combined CODEC unit. The architecture is fully scalable allowing any number of bytes or words to be encoded or decoded in parallel. The number of 8B10B ENCODER bytes and words are specified by the nb and nw generic parameters. Pin name I/O Description Active state The encoder and decoder feature a simple synchronous user interface. clk in System clock rising edge Data inputs and flags are sampled on the rising-edge of clk when the (Synchronous with parallel datain val signal is active high. Likewise, data outputs and flags are valid input data) on the rising-edge of clk when dataout val is active high. reset in Asynchronous reset low As well as regular 8-bit data, the encoder can accept one of the special control characters or symbols. These symbols are labelled K.28.0 to datain in N x input data bytes data K.30.7 and, by convention, are used to insert commas and control nb * 8 - 1:0 characters in a transmitted bitstream. The table below shows the datain k in N x control byte enables high standard symbols supported: nb - 1:0 (Indicates that byte is a control symbol) Current RD -ve Current RD +ve datain val in Input data valid high Input HGFEDCBA abcdeifghj abcdeifghj K.28.0 00011100 0011110100 1100001011 dataout out N x 10-bit output data data nb * 10 - 1:0 words K.28.1 00111100 0011111001 1100000110 dataout kerr out N x control byte error flags high K.28.2 01011100 0011110101 1100001010 nb - 1:0 (Indicates an unrecognised control symbol input) K.28.3 01111100 0011110011 1100001100 K.28.4 10011100 0011110010 1100001101 dataout rd out Output running disparity high: surplus of flag 1s K.28.5 10111100 0011111010 1100000101 low: surplus of 0s K.28.6 11011100 0011110110 1100001001 dataout val out Output data valid high K.28.7 11111100 0011111000 1100000111 K.23.7 11110111 1110101000 0001010111 K.27.7 11111011 1101101000 0010010111 8B10B DECODER K.29.7 11111101 1011101000 0100010111 Pin name I/O Description Active state K.30.7 11111110 0111101000 1000010111 clk in System clock rising edge (Synchronous with parallel input data) In order to specify that the data input to the encoder is a control symbol then the signal datain k should be set appropriately. Setting this bit high reset in Asynchronous reset low in the respective byte position will make the encoder interpret the input as a control symbol. If the control symbol is not recognized then the encoder datain in N x 10-bit input data words data will assert the dataout kerr signal with the respective output data. nw * 10 - 1:0 The decoder has a reciprocal operation to the encoder and decodes the N datain val in Input data valid high x 10-bit data back to the original N x bytes. If the decoder detects a decoding error in the stream then the dataout kerr flag will be asserted high for the respective byte. dataout out N x output data bytes data nw * 8 - 1:0 All Running Disparity (RD) calculations are handled internally in the dataout k out N x control byte flags high encoder core. In addition, the current RD is provided as an output flag nw -1:0 (Indicates that byte is a from the encoder. Resetting the encoder will initialize the current running control symbol) disparity to zero by default. In addition, the current RD is also provided as an output flag for use by downstream devices. Both the encoder and dataout kerr out N x decoding error flags high decoder have a latency of 1 clock cycle from input valid to output valid. nw - 1:0 (Indicates an error in the decoded output byte) dataout val out Output data valid high Functional Timing Figure 2 below shows an example series of three consecutive bytes being encoded. The third byte in the sequence is specified as a control symbol General Description by asserting the datain k flag high. Inputs are sampled on the rising edge of clk when datain val is high. The CODEC 8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair Inputs are ignored otherwise. The encoder has a latency of 1 clock cycle suitable for a wide range of serial data transmission applications. The from input to output. design is optimized for very high-speed operation and is suitable for use in serial data links of 6 GHz+ on basic FPGA devices. Copyright 2020 www.zipcores.com Download this IP Core Page 2 of 4