XQ UltraScale Architecture Data Sheet: Overview DS895 (v2.1) July 9, 2021 Product Specification General Description The Defense-grade XQ UltraScale architecture-based devices extend the equivalent commercial offerings, adding unique ruggedized packages, extended operating temperature range support, and added environmental qualification testing. This XQ portfolio spans the following families, with each offering a unique mix of features. XQ Kintex UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost. XQ Kintex UltraScale+ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope. XQ Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope. XQ Zynq UltraScale+ MPSoCs: Combine the Arm v8-based Cortex-A53 high-performance energy-efficient 64-bit application processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry s first Defense-grade MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration. XQ Zynq UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure. XQ Device Comparisons (1) Table 1: Device Resources XQ Kintex XQ Kintex XQ Virtex XQ Zynq XQ Zynq UltraScale UltraScale+ UltraScale+ UltraScale+ UltraScale+ FPGA FPGA FPGA MPSoC RFSoC MPSoC Processing System RF-ADC/DAC and SD-FEC System Logic Cells (K) 5301,451 4751,143 8622,835 1541,143 930 Block Memory (Mb) 21.175.9 16.934.6 25.370.9 5.134.6 38.0 UltraRAM (Mb) 1836 90270 036 22.5 (2) HBM DRAM (GB) 0 DSP (Slices) 1,9205,520 1,8241,968 2,2809,216 3603,528 4,272 (3) DSP Performance (GMAC/s) 7,297 3,050 14,284 5,468 6,621 Transceivers 1664 1656 4096 048 816 Max. Transceiver Speed (Gb/s) 16.3 28.2 28.2 28.2 28.2 Max. Serial Bandwidth (full duplex) (Gb/s) 2,086 2,402 5,416 1,950 902 I/O Pins 312728 280512 416832 82644 152408 Notes: 1. Metrics given in this table pertain to the XQ ruggedized package devices. For non-ruggedized device variants consult Xilinx sales. 2. HBM not currently offered in an XQ ruggedized Package consult Xilinx sales for further details and options. 3. Calculated based on XQ maximum DSP clock rate for a Symmetric FIR Filter, e.g. for KU040 with 1920 DSP48s, -2 speed-grade DSP48 F =661MHz, GMACs=2x0.661x1,920=2,538. MAX Copyright 20172021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, UltraScale, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of Arm in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. 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DS895 (v2.1) July 9, 2021 www.xilinx.com Product Specification 1XQ UltraScale Architecture Data Sheet: Overview Table 2: XQ Zynq UltraScale+ MPSoC and RFSoC Processor System Features MPSoC RFSoC EG Devices EV Devices DR Devices APU Quad-core Arm Cortex-A53 Quad-core Arm Cortex-A53 Quad-core Arm Cortex-A53 RPU Dual-core Arm Cortex-R5F Dual-core Arm Cortex-R5F Dual-core Arm Cortex-R5F GPU Mali-400MP2 Mali-400MP2 VCU H.264/H.265 Key Defense-grade Ruggedized Package Features Ruggedized packaging MIL-STD-883 group D Qualification testing Military (M) temperature support of 55C to +125C (optionally available) Full range extended temperature testing Mask set control Full compliance with MIL-PRF-38535 Pb content standards Longer-term availability Anti-counterfeiting features Available information assurance (IA) methodology Available anti-tamper (AT) technology Ruggedized Packaging XQ ruggedized packages have a unique 4-corner lid that has wider vent openings around the periphery. This lid simplifies the board-level assembly process for applications requiring conformal coating. In the conformal coating process, boards go through a caustic etching process to achieve the required conformal coating adherence. The caustic etching material or other corrosive chemicals can become trapped inside of non-ruggedized packaging, leading to reliability concerns with flip-chip packaging. With the XQ ruggedized package, the 4-corner lid significantly simplifies cleaning and manufacturing process, allowing the device to be fully flushed prior to sealing the device/board with conformal coating. MIL-STD-883 group D specification stress testing is completed prior to production release of the defense grade (XQ) devices. Qualification reports are available for the XQ UltraScale architecture ruggedized devices. MIL-STD-883 group D Qualification testing for Defense-grade products includes the following: Physical dimensions (TM 2016) Thermal shock (TM 1011 condition B 15 cycles) Temperature cycling (TM 1010 condition C 100 cycles) Moisture Resistance (TM 1004) Vibration - Variable Frequency (TM 2007 Condition A minimum) Constant Acceleration - Centrifuge (TM 2001 Condition D minimum - Y1 orientation only) Salt Atmosphere (TM 1009 Condition A minimum) DS895 (v2.1) July 9, 2021 www.xilinx.com Product Specification 2