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XC9572XL-7TQG100I

Name: XC9572XL-7TQG100I
Brand: Xilinx
SKU: XC9572XL7TQG100I_Xilinx
Availability: OutOfStock
Rating: 5 (11 reviews)

XC9572XL-7TQG100I electronic component of Xilinx

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CPLD, 72 I/O, -40 TO 85DEG C; CPLD Type:FLASH; No. of Macrocells:72; No. of I/O's:72I/O's; Logic Case Style:TQFP; No. of Pins:100Pins; Frequency:125MHz; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Propagation Delay:7.5ns; Global Clock Setup Time:4.8ns; Operating Temperature Min:-40C; Operating Temperature Max:85C; Product Range:XC9572XL Series; SVHC:No SVHC (27-Jun-2018)

Manufacturer: Xilinx

This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

1: USD 29.6217 ea
Line Total: USD 29.62

0 - Global Stock

MOQ: 1 Multiples: 1
Pack Size: 1

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Availability	Price	Buy Price	Quantity
0 - Global Stock Ships to you between Fri. 03 May to Thu. 09 May MOQ : 1 Multiples : 1 XC9572XL-7TQG100I Xilinx	1 : USD 29.6217

0 - Global Stock Ships to you between Fri. 03 May to Thu. 09 May MOQ : 1 Multiples : 1 XC9572XL-7TQG100I Xilinx	1 : USD 22.9097

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Additional Infomation About Product

0 R XC9572XL High Performance CPLD 00 DS057 (v2.0) April 3, 2007 Product Specification cations and computing systems. It is comprised of four Features 54V18 Function Blocks, providing 1,600 usable gates with 5 ns pin-to-pin logic delays propagation delays of 5 ns. See Figure 2 for overview. System frequency up to 178 MHz Power Estimation 72 macrocells with 1,600 usable gates Available in small footprint packages Power dissipation in CPLDs can vary substantially depend- - 44-pin PLCC (34 user I/O pins) ing on the system frequency, design application and output - 44-pin VQFP (34 user I/O pins) loading. To help reduce power dissipation, each macrocell - 48-pin CSP (38 user I/O pins) in a XC9500XL device may be configured for low-power - 64-pin VQFP (52 user I/O pins) mode (from the default high-performance mode). In addi- - 100-pin TQFP (72 user I/O pins) tion, unused product-terms and macrocells are automati- cally deactivated by the software to further conserve power. - Pb-free available for all packages Optimized for high-performance 3.3V systems For a general estimate of I , the following equation may be CC - Low power operation used: - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V I (mA) = MC (0.175*PT + 0.345) + MC (0.052*PT CC HS HS LP LP signals + 0.272) + 0.04 * MC (MC +MC )* f TOG HS LP - 3.3V or 2.5V output capability where: - Advanced 0.35 micron feature size CMOS MC = macrocells in high-speed configuration HS Fast FLASH technology PT = average number of high-speed product terms HS Advanced system features per macrocell - In-system programmable MC = macrocells in low power configuration LP - Superior pin-locking and routability with PT = average number of low power product terms per LP Fast CONNECT II switch matrix macrocell - Extra wide 54-input Function Blocks f = maximum clock frequency - Up to 90 product-terms per macrocell with MCTOG = average % of flip-flops toggling per clock individual product-term allocation (~12%) - Local clock inversion with three global and one This calculation was derived from laboratory measurements product-term clocks of an XC9500XL part filled with 16-bit counters and allowing - Individual output enable per output pin a single output (the LSB) to be enabled. The actual I CC - Input hysteresis on all user and boundary-scan pin value varies with the design application and should be veri- inputs fied during normal system operation. Figure 1 shows the - Bus-hold circuitry on all user pin inputs above estimation in a graphical form. For a more detailed - Full IEEE Standard 1149.1 boundary-scan (JTAG) discussion of power consumption in this device, see Xilinx Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package WARNING: Programming temperature range of T = 0 C to +70 C A Description The XC9572XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XC9572XL High Performance CPLD application note XAPP114, Understanding XC9500XL CPLD Power. 125 178 MHz 100 75 104 MHz 50 25 0 50 100 150 200 Clock Frequency (MHz) DS057 01 010102 Figure 1: Typical I vs. Frequency for XC9572XL CC 3 JTAG In-System Programming Controller 1 JTAG Port Controller 54 Function 18 I/O Block 1 Macrocells I/O 1 to 18 I/O 54 I/O Function 18 Block 2 Macrocells 1 to 18 I/O Blocks I/O 54 Function I/O 18 Block 3 I/O Macrocells 1 to 18 I/O 3 I/O/GCK 54 Function 1 18 I/O/GSR Block 4 2 Macrocells I/O/GTS 1 to 18 DS057 02 082800 Figure 2: XC9572XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification High Performance r Low Powe Typical I (mA) CC Fast CONNECT II Switch Matrix

HS Compliance

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:

Xilinx may also be referenced as

XI4
XILINX
Xilinx Inc
Xilinx Inc.

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