52 Virtex-6 CXT Family Data Sheet DS153 (v1.6) February 11, 2011 Product Specification General Description Virtex-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1 slices, enhanced mixed-mode clock management blocks, PCI Express (GEN 1) compatible integrated blocks, a tri-mode Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains SelectIO technology with built-in digitally controlled impedance, ChipSync source-synchronous interface blocks, enhanced mixed-mode clock management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Summary of Virtex-6 CXT FPGA Features Advanced, high-performance, FPGA Logic Advanced DSP48E1 slices Real 6-input look-up table (LUT) technology 25 x 18, two s complement multiplier/accumulator Dual LUT5 (5-input LUT) option Optional pipelining LUT/dual flip-flop pair for applications requiring rich New optional pre-adder to assist filtering applications register mix Optional bitwise logic functionality Improved routing efficiency Dedicated cascade connections 64-bit (or 32 x 2-bit) distributed LUT RAM option Flexible configuration options SRL32/dual SRL16 with registered outputs option SPI and Parallel Flash interface Powerful mixed-mode clock managers (MMCM) Multi-bitstream support with dedicated fallback MMCM blocks provide zero-delay buffering, frequency reconfiguration logic synthesis, clock-phase shifting, input-jitter filtering, and Automatic bus width detection phase-matched clock division Integrated interface blocks for PCI Express designs 36-Kb block RAM/FIFOs Compliant to the PCI Express Base Specification 2.0 Dual-port RAM blocks Gen1 Endpoint (2.5 Gb/s) support with GTX transceivers Programmable x1, x2, x4, or x8 lane support per block - Dual-port widths up to 36 bits One virtual channel, eight traffic classes - Simple dual-port widths up to 72 bits GTX transceivers: 150 Mb/s to 3.75 Gb/s Enhanced programmable FIFO logic Integrated 10/100/1000 Mb/s Ethernet MAC block Built-in optional error-correction circuitry Supports 1000BASE-X PCS/PMA and SGMII using Optionally use each block as two independent 18 Kb GTX transceivers blocks Supports MII, GMII, and RGMII using SelectIO High-performance parallel SelectIO technology technology resources 1.2 to 2.5V I/O operation 40 nm copper CMOS process technology Source-synchronous interfacing using 1.0V core voltage ChipSync technology Two speed grades (-1 and -2) Digitally controlled impedance (DCI) active termination Two temperature grades (commercial and industrial) Flexible fine-grained I/O banking High signal-integrity flip-chip packaging available in standard High-speed memory interface support with integrated or Pb-free package options write-leveling capability Compatibility across sub-families: CXT, LXT, and SXT devices are footprint compatible in the same package 20092011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS153 (v1.6) February 11, 2011 www.xilinx.com Product Specification 1Virtex-6 CXT Family Data Sheet Virtex-6 CXT FPGA Feature Summary Table 1: Virtex-6 CXT FPGA Feature Summary by Device Configurable Logic Block RAM Blocks Blocks (CLBs) Interface Maximum Total Max Logic DSP48E1 Ethernet (4) Device MMCMs Blocks for GTX I/O User (2) (5) Cells Max Slices MACs (6) (7) PCI Express Transceivers Banks I/O (1) (3) Slices Distributed 18 Kb 36 Kb Max (Kb) RAM (Kb) XC6VCX75T 74,496 11,640 1,045 288 312 156 5,616 6 1 1 12 9 360 XC6VCX130T 128,000 20,000 1,740 480 528 264 9,504 10 2 1 16 15 600 XC6VCX195T 199,680 31,200 3,040 640 688 344 12,384 10 2 1 16 15 600 XC6VCX240T 241,152 37,680 3,650 768 832 416 14,976 12 2 1 16 18 600 Notes: 1. Each Virtex-6 CXT FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs. 2. Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks. 4. Each CMT contains two mixed-mode clock managers (MMCM). 5. This table lists individual Ethernet MACs per device. 6. Does not include configuration Bank 0. 7. This number does not include GTX transceivers. Virtex-6 CXT FPGA Device-Package Combinations and Maximum I/Os Virtex-6 CXT FPGA package combinations with the maximum available I/Os per package are shown in Table 2. Table 2: Virtex-6 CXT FPGA Device-Package Combinations and Maximum Available I/Os FF484 FF784 FF1156 Package FFG484 FFG784 FFG1156 Size (mm) 23x23 29x29 35x35 Device GTs I/O GTs I/O GTs I/O XC6VCX75T 8 GTXs 240 12 GTXs 360 XC6VCX130T 8 GTXs 240 12 GTXs 400 16 GTXs 600 XC6VCX195T 12 GTXs 400 16 GTXs 600 XC6VCX240T 12 GTXs 400 16 GTXs 600 Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). Virtex-6 CXT FPGA Ordering Information The Virtex-6 CXT FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free. X-Ref Target - Figure 1 Example: XC6VCX240T-1FFG1156C Device Type Temperature Range: Speed Grade C = Commercial (T = 0C to +85C) J (-1, -2) I = Industrial (T = 40C to +100C) J Number of Pins Pb-Free Package Type DS153 01 062109 Figure 1: Virtex-6 CXT FPGA Ordering Information DS153 (v1.6) February 11, 2011 www.xilinx.com Product Specification 2