LTE Fast Fourier Transform v2.0 PB023 (v2.0) April 5, 2017 LogiCORE IP Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Xilinx LogiCORE IP LTE Fast Fourier UltraScale+ Families Transform (FFT) implements all transform Supported UltraScale Architecture (1) Device Family Zynq-7000 All Programmable SoC lengths required by the 3GPP LTE specification, 7 Series including the 1536-point transform for 15 MHz Supported User bandwidth support. Not Applicable Interfaces Provided with Core Additional Documentation Design Files Encrypted RTL Example Design Not Provided A full product guide is available for this core. Test Bench Not Provided Access to this material can be requested by clicking on this registration link: Constraints File Not Provided www.xilinx.com/member/lte fft eval/index.htm Simulation Encrypted VHDL Model C Model Supported Not Applicable Features S/W Driver (2) Tested Design Flows Forward and inverse complex FFT, run-time Design Entry Vivado Design Suite configurable For supported simulators, see the Simulation Supports transform point sizes 128, 256, Xilinx Design Tools: Release Notes Guide. 512, 1024, 1536, 2048 Synthesis Vivado Synthesis Data sample precision b = 14 17 Support x Provided by Xilinx at the Xilinx Support web page Phase factor precision b = 14 17 w Notes: Optional run-time configurable point size 1. For a complete list of supported devices, see the Vivado IP catalog. Run-time configurable fixed scaling 2. For the supported versions of the tools, see the schedule, or unscaled datapath Xilinx Design Tools: Release Notes Guide Bit/digit reversed or natural output order Optional cyclic prefix insertion Four architectures offer a trade-off between core size and transform time Copyright 20142017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. LTE Fast Fourier Transform v2.0 1 Send Feedback PB023 (v2.0) April 5, 2017 www.xilinx.comProduct Brief Applications The LTE FFT IP core can be used to implement the Fast Fourier Transform requirements of the 3GPP LTE standard. The core can be used to implement both inverse FFT for the downlink and direct FFT for the uplink. The core is a component of the Xilinx LTE Baseband Targeted Design Platform. Overview The LTE FFT core computes an N-point forward DFT or inverse DFT where N can be 128, 256, 512, 1024, 1536, 2048. The input data is a vector of N complex values represented as dual b -bit twos-complement x numbers, that is, b bits for each of the real and imaginary components of the data sample, where x b is in the range 14 to 17 bits inclusive. Similarly, the phase factors b can be 14 to 17 bits wide. x w The N element output vector is represented using b bits for each of the real and imaginary x components of the output data. Input data is presented in natural order and the output data can be in either natural or bit/digit reversed order. Two arithmetic options are available for computing the FFT: Full-precision unscaled arithmetic Scaled fixed-point arithmetic, with a user-specified scaling schedule The point size N, the choice of forward or inverse transform, the scaling schedule and the cyclic prefix length are run-time configurable. Transform type (forward or inverse), scaling schedule and cyclic prefix length can be changed on a frame-by-frame basis. Changing the point size immediately resets the core. Four architecture options are available: Pipelined, Streaming I/O Radix-4, Burst I/O Radix-2, Burst I/O Radix-2 Lite, Burst I/O LTE Fast Fourier Transform v2.0 2 Send Feedback PB023 (v2.0) April 5, 2017 www.xilinx.com