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VCS1625ZP (Z-Foil) Vishay Foil Resistors Ultra High Precision Z-Foil Surface Mount Current Sensing Chip Resistor with Power Rating to 1 W and Temperature Coefficient of Resistance of 0.05 ppm/C and Power Coefficient of 5 ppm at Rated Power FEATURES Temperature coefficient of resistance (TCR): NEW 0.05 ppm/C typical (0 C to + 60 C) 0.2 ppm/C typical (- 55 C to + 125 C, + 25 C ref.) (see table 1) Resistance range: 0.3 to 10 (for higher or lower values please contact us) Vishay Foil Resistors are not restricted to standard values, INTRODUCTION we can supply specific as required values at no extra cost The Z-foil technology provides a significant increase of or delivery (e.g. 1.234 vs. 1 ) stability of resistance values sensitivity to ambient Resistance Tolerance: to 0.2% (0.05% and 0.1% are temperature variations (TCR) and applied power changes also available) (PCR). Designers can now guarantee a high degree of Power coefficient R due to self heating: 5 ppm at rated stability and accuracy in fixed-resistor applications using power solutions based on VPGs revolutionary Z-foil technology. Load life stability: 0.015 % at 70 C, 2000 h at rated power Electrostatic discharge (ESD) at least to 25 000 V Model VCS1625ZP is a surface mount chip resistor designed Short time overload < 0.005 % with 4 pads for Kelvin connection. Utilizing VPGs Bulk Thermal stabilization time < 1 s (nominal value achieved Metal Z-foil as the resistance element, it provides within 10 ppm of steady state value) performance capabilities far greater than other resistor Power rating: 1 W at + 70 C (figure 1) technologies can supply in a product of comparable size. Non inductive, non capacitive design 0.05 ppm/C typical TCR removes errors due to temperature gradients. Rise time: 1 ns effectively no ringing Current rating: 1.8 A maximum This small device dissipates heat almost entirely through the Current noise: 0.010 V /V of applied voltage(< - 40 dB) RMS pads so surface mount users are encouraged to be generous Voltage coefficient: < 0.1 ppm/V with the boards pads and traces. Non inductive: < 0.08 H The four terminal device separates the current leads from the Non hot spot design voltage sensing leads. This configuration eliminates the Prototype quantities available in just 5 working days or effect of the lead wire resistance from points A to B and C to sooner. D, allowing low TCR current sensing. For higher temperature application above +150 C and for better performances please contact us. FIGURE 1 - POWER DERATING CURVE TERMINATIONS Two lead (Pb)-free options are available: - 55 C + 70 C gold plated or tin plated 100 Tin/lead plated 75 BC 50 R I I 25 0 A D - 75 - 50 - 25 0 + 25 + 50 + 75 + 100 + 125 + 150 + 175 V Ambient Temperature (C) ~ Zin = (1) TABLE 1 - SPECIFICATIONS MODEL RESISTANCE RESISTANCE TYPICAL TCR and MAX. SPREAD POWER RATING MAXIMUM (4) (2) (2) NUMBER RANGE TOLERANCE (- 55 C to + 125 C, + 25 C Ref) at + 70 C CURRENT > 2.0 to 10 0.2 %, 0.5 % 1.0 % (3) VCS1625ZP 0.2 2.8 ppm/C 1 W on FR4 PCB 1.8 A 0.3 to 2.0 0.5 % 1.0 % Notes (1) Tighter performances are available. Please contact application engineering foil vishaypg.com (2) Whichever is lower (3) See solder pad layout at figure 2 (4) 0.05% and 0.1% are also available per special request * Pb containing materials are not RoHS compliant, exemptions may apply Document Number: 63155 For any questions, contact: foil vishaypg.com www.vishayfoilresistors.com Revision: 24-Jan-13 1 Percent of Rated PowerVCS1625ZP (Z-Foil) Vishay Foil Resistors FIGURE 2 - DIMENSIONS in Inches (Millimeters) Solder Pad Layout 2 oz. Copper (70 Microns) 0.806 (20.47) Coated by Solder mask 0.020 (0.51) Mounting A Electrical L W Pads (4) Schematic I E 1 1 B I E 1 1 H R I E 2 2 Top View I E 2 2 Bottom View 0.070 (1.78) Solder Coated Pads 0.260 (6.60) (Windows in Solder Mask) INCHES MILLIMETERS L 0.250 0.010 6.35 0.25 H 0.160 0.010 4.06 0.25 W 0.040 maximum 1.02 maximum A 0.080 0.005 2.03 0.13 B 0.040 0.010 1.02 0.25 FIGURE 3 - TRIMMING TO VALUES FIGURE 4 - TYPICAL TCR CURVE Z-FOIL (Conceptual Illustration)* + 500 + 400 + 300 Current Path Interloop Capacitance Before Trimming + 200 Reduction in Series + 100 R 0 Current Path R (ppm) After Trimming - 100 0.05 ppm/C Mutual Inductance Trimming Process Reduction due - 200 Removes this Material - 0.1 ppm/C 0.1 ppm/C to Opposing from Shorting Strip Area Current in - 300 0.14 ppm/C Changing Current Path Adjacent Lines - 400 and Increasing - 0.16 ppm/C 0.2 ppm/C Resistance - 500 - 55 - 25 0 + 25 + 60 + 75 + 100 + 125 Ambient Temperature (C) Note: Foil shown in black, etched spaces in white * To acquire a precision resistance value, the Bulk Metal Foil chip is trimmed by selectively removing built-in shorting bars. To increase the resistance in known increments, marked areas are cut, producing progressively smaller increases in resistance. This method eliminates the effect of hot spot and improves the long term stability of the hybrid chips. TABLE 2 - PERFORMANCE SPECIFICATIONS MIL-PRF-55342 TYPICAL MAXIMUM TEST (1) R LIMITS R LIMITS R LIMITS Thermal shock 5 x (- 65 C to + 150 C) 0.10 % 0.005 % (50 ppm) 0.01 % (100 ppm) Low temperature operation, - 65 C, 45 min at P 0.10 % 0.005 % (50 ppm) 0.01 % (100 ppm) nom Short time overload, 6.25 x rated power, 5 s 0.10 % 0.005 % (50 ppm) 0.02 % (200 ppm) High temperature exposure, + 150 C, 100 h 0.10 % 0.01 % (100 ppm) 0.02 % (200 ppm) Resistance to soldering heat 0.2 % 0.01 % (100 ppm) 0.03 % (300 ppm) Moisture resistance 0.2 % 0.01 % (100 ppm) 0.03 % (300 ppm) Load life stability 2000 h at 70 C at 1 W 0.5 % 0.015 % (150 ppm) 0.025 % (250 ppm) Note (1) Measurement error 0.001R www.vishayfoilresistors.com For any questions, contact: foil vishaypg.com Document Number: 63155 2 Revision: 24-Jan-13 0.200 (5.08) 0.070 (1.78) 0.020 (0.51) 0.806 (20.47)