TC74VHCT138AF/AFT/AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT138AF, TC74VHCT138AFT, TC74VHCT138AFK 3-to-8 Line Decoder TC74VHCT138AF The TC74VHCT138 is an advanced high speed CMOS 3-to-8 2 LINE DECODER fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 to Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. TC74VHCT138AFT G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can (Note) be applied to the input and output pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as TC74VHCT138AFK battery back up, hot board insertion, etc. Note: V = 0 V CC Features High speed: t = 7.6 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Compatible with TTL inputs: V = 0.8 V (max) IL V = 2.0 V (min) IH Weight Power down protection is provided on all inputs and outputs SOP16-P-300-1.27A: 0.18 g (typ.) Balanced propagation delays: t t pLH pHL TSSOP16-P-0044-0.65A: 0.06 g (typ.) Pin and function compatible with the 74 series VSSOP16-P-0030-0.50: 0.02 g (typ.) (74AC/HC/F/ALS/LS etc.) 138 type. Start of commercial production 1995-12 1 2014-03-01 TC74VHCT138AF/AFT/AFK Pin Assignment A 1 16 V CC B 2 15 Y0 C 14 Y1 3 G 2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 (top view) IEC Logic Symbol BIN/OCT DMUX (1) (15) (1) (15) A 1 0 Y0 A 0 0 Y0 0 (2) (14) (2) (14) B 2 1 Y1 B G 1 Y1 7 (3) (13) (3) (13) C 4 2 Y2 C 2 2 Y2 (12) (12) 3 Y3 3 Y3 (11) (11) 4 Y4 4 Y4 & & (6) (10) (6) (10) G1 5 Y5 G1 5 Y5 (4) (9) (4) (9) G2A EN 6 Y6 G2A 6 Y6 (5) (7) (5) (7) G2B 7 Y7 G2B 7 Y7 Truth Table Inputs Outputs Selected Enable Select Output Y0 Y1 Y2 Y3 Y4 Y5 Y 6 Y 7 G1 G2A G2B C B A L X X X X X H H H H H H H H None X H X X X X H H H H H H H H None X X H X X X H H H H H H H H None H L L L L L L H H H H H H H Y 0 H L L L L H H L H H H H H H Y 1 H L L L H L H H L H H H H H Y 2 H L L L H H H H H L H H H H Y 3 H L L H L L H H H H L H H H Y 4 H L L H L H H H H H H L H H Y 5 H L L H H L H H H H H H L H Y 6 H L L H H H H H H H H H H L Y 7 X: Dont care 2 2014-03-01